|CXL5508M||CMOS-CCD 1H Delay Line for PAL|
|CXL5508M Datasheet PDF : 9 Pages |
(1) This is the IC supply current value during clock and signal input.
(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log OUT pin output voltage [mVp-p] [dB]
(3) Indicates the dissipation at 2MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, cal culation is made
according to the following formula. Input bias is tested at 2.1V.
OUT pin otuput voltage (2MHz) [mVp-p]
fg = 20 log
OUT pin output voltage (200kHz) [mVp-p]
(4) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. Input bias is tested at 2.1V.
(5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is
calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following
S/N = –20 • Iog 0.5 • 10 GL/20 [dB]
(6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance
signals only) and calculated according to the formula below.
(However, output signals become inverted with regards to input.)
LIS = Vs × 100 [%]
LIC = Vc × 100 [%]
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