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TS68C429AMRA View Datasheet(PDF) - Unspecified

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TS68C429AMRA Datasheet PDF : 46 Pages
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TS68C429A
5. Requirements
5.1 General
The microcircuits are in accordance with the applicable document and as specified herein.
5.2 Design and Construction
5.2.1
Terminal Connections
Depending on the package, the terminal connections is detailed in “Terminal Connections” on page 42.
5.2.2
Package
The circuits are packaged in a hermetically sealed ceramic package which is conform to case outlines of
MIL-STD 1835 (when defined):
• PGA 84,
• CQFP 132.
The precise case outlines are described at the end of this specification (“Package Mechanical Data” on
page 41) and into MIL-STD-1835.
5.2.3
Special Recommended Conditions for CMOS Devices
• CMOS Latch-up
The CMOS cell is basically composed of two complementary transistors (a P-channel and an N-chan-
nel), and, in the steady state, only one transistor is turned-on. The active P-channel transistor sources
current when the output is a logic high and presents a high impedance when the output is a logic low.
Thus the overall result is extremely low power consumption because there is no power loss through the
active P-channel transistor. Also since only once transistor is determined by leakage currents.
Because the basic CMOS cell is composed of two complementary transistors, a parasitic semiconductor
controlled rectifier (SCR) formed and may be triggered when an input exceeds the supply voltage. The
SCR that is formed by this high input causes the device to become “latched” in a mode that may result in
excessive current drain and eventual destruction of the device. Although the device is implemented with
input protection diodes, care should be exercised to ensure that the maximum input voltages specifica-
tion is not exceeded from voltage transients; others may require no additional circuitry.
• CMOS/TTL Levels
The TS68C429A doesn’t satisfy totally the input/output drive requirements of TTL logic devices, see
Table 7-1 on page 11.
e2v semiconductors SAS 2008
7
0848E–HIREL–02/08
 

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