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MC33882FC View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
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MC33882FC
Freescale
Freescale Semiconductor Freescale
MC33882FC Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Freescale Semiconductor, Inc.
VPWR
1
IN0 & IN1
2
MODE
3
IN0
4
OUT0
5
IN1
6
OUT1
7
NC
8
IN2
9
OUT2
10
NC
11
SI
12
SCLK
13
CS
14
SO
15
HEAT
SINK
30
OUT6
29
IN6
28
IN4 & IN5
27
IN5
26
OUT5
25
NC
24
IN4
23
OUT4
22
NC
21
IN3
20
OUT3
19
IN2 & IN3
18
IN7
17
OUT7
16
VDD
HSOP TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
1
VPWR
Load Supply Voltage
2
IN0 & IN1
Input 0 & Input 1
19
IN2 & IN3
Input 2 & Input 3
28
IN4 & IN5
Input 4 & Input 5
3
4
6
9
18
21
24
27
29
5
7
10
17
20
23
26
30
8, 11, 22, 25
12
MODE
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
NC
SI
Mode Select
Input 0–Input7
Output 0–Output7
No Connect
Serial Input
13
SCLK
Serial Clock
14
CS
Chip Select
Definition
This terminal is connected to battery voltage. A decoupling cap is required from VPWR
to ground.
These input terminals control two output channels each when the MODE terminal is
pulled high. These terminals may be connected to pulse width modulated (PWM)
outputs of the control IC while the MODE terminal is high. The states of these terminals
are ignored during normal operation (MODE terminal low) and override the normal
inputs (serial or parallel) when the MODE terminal is high. These terminals have
internal active 25 µA pull-downs.
The MODE terminal is connected to the MODE terminal of the control IC. This terminal
has an internal active 25 µA pull-up.
These are parallel control input terminals. These terminals have internal 25 µA active
pull-downs.
Each terminal is one channel's drain, sinking current for the respective load.
Not connected.
The Serial Input terminal is connected to the SPI Serial Data Output terminal of the
control IC from where it receives output command data. This input has an internal
active 25 µA pull-down and requires CMOS logic levels.
The SCLK terminal of the control IC is a bit (shift) clock for the SPI port. It transitions
one time per bit transferred when in operation. It is idle between command transfers. It
is 50% duty cycle, and has CMOS levels.
This terminal is connected to a chip select output of the control IC. This input has an
internal active 25 µA pull-up and requires CMOS logic levels.
MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDEoVrIeCEIDnAfoTArmation On This Product,
Go to: www.freescale.com
33882
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