M12L64164A-6TA View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.

Part Name

Description

View to exact match

M12L64164A-6TA

1M x 16 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L64164A

Operation temperature condition -25℃ ~ 85℃

COMMANDS

Mode register set command

( CS , RAS , CAS , WE = Low)

The M12L64164A has a mode register that defines how the device operates. In

this command, A0 through A13 are the data input pins. After power on, the mode

register set command must be executed to initialize the device.

The mode register can be set only when all banks are in idle state. During 2CLK

(tRSC) following this command, the M12L64164A cannot accept any other commands.

Activate command

( CS , RAS = Low, CAS , WE = High)

The M12L64164A has four banks, each with 4,096 rows.

This command activates the bank selected by A12 and A13 (BS) and a row

address selected by A0 through A11.

This command corresponds to a conventional DRAM’s RAS falling.

CLK

CKE

H

CS

RAS

CAS

WE

A12, A13

A10

Add

Fig. 1 Mode register set

command

CLK

CKE

H

CS

RAS

CAS

WE

A12, A13

(Bank select)

A10

Add

Row

Row

Fig. 2 Row address stroble and

bank active command

Precharge command

( CS , RAS , WE = Low, CAS = High )

This command begins precharge operation of the bank selected by A12 and A13

(BS). When A10 is High, all banks are precharged, regardless of A12 and A13. When

A10 is Low, only the bank selected by A12 and A13 is precharged.

After this command, the M12L64164A can’t accept the activate command to the

precharging bank during tRP (precharge to activate command period).

This command corresponds to a conventional DRAM’s RAS rising.

CLK

CKE

H

CS

RAS

CAS

WE

A12, A13

(Bank select)

A10

(Precharge select)

Add

Fig. 3 Precharge command

Elite Semiconductor Memory Technology Inc.

Publication Date: Dec. 2004

Revision: 0.1

14/44

Share Link: