M12L64164A View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L64164A

1M x 16 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

Write command

( CS , CAS , WE = Low, RAS = High)

If the mode register is in the burst write mode, this command sets the burst start

address given by the column address to begin the burst write operation. The first

write data in burst can be input with this command with subsequent data on following

clocks.

M12L64164A

Read command

( CS , CAS = Low, RAS , WE = High)

Read data is available after CAS latency requirements have been met.

This command sets the burst start address given by the column address.

CBR (auto) refresh command

( CS , RAS , CAS = Low, WE , CKE = High)

This command is a request to begin the CBR refresh operation. The refresh

address is generated internally.

Before executing CBR refresh, all banks must be precharged.

After this cycle, all banks will be in the idle (precharged) state and ready for a

row activate command.

During tRFC period (from refresh command to refresh or activate command), the

M12L64164A cannot accept any other command.

Elite Semiconductor Memory Technology Inc.

Publication Date: May 2009

Revision: 3.4

14/45

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