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AD9694BCPZ-500 View Datasheet(PDF) - Analog Devices

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Description
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AD9694BCPZ-500 Datasheet PDF : 101 Pages
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Data Sheet
AD9694
Parameter
LATENCY5
Pipeline Latency
Fast Detect Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tj)
Out of Range Recovery Time
Min
Typ
Max
Unit
54
Sample clock cycles
30
Sample clock cycles
160
ps
44
fs rms
1
Sample clock cycles
1 The maximum sample rate is the clock rate after the divider.
2 The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. See SPI Register 0x011A to reduce the threshold of the clock detect circuit.
3 Baud rate = 1/UI. A subset of this range can be supported.
4 Default L = 2 for each link. This number can be changed based on the sample rate and decimation ratio.
5 No DDCs used. L = 2, M = 2, F = 2 for each link.
TIMING SPECIFICATIONS
Table 7.
Parameter
CLK+ to SYSREF+ TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
tDIS_SDIO
Test Conditions/Comments
See Figure 3
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
See Figure 4
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
Time required for the SDIO pin to switch from an output to an
input relative to the CSB rising edge (not shown in Figure 4)
Timing Diagrams
APERTURE
DELAY
ANALOG
INPUT
SIGNAL
N – 54
N – 53
N – 52
N – 51
N – 50
SAMPLE N
N+1
N–1
Min Typ Max Unit
−44.8
ps
64.4
ps
4
2
40
2
2
10
10
6
10
ns
ns
ns
ns
ns
ns
ns
10 ns
ns
CLK–
CLK+
CLK–
CLK+
SYSREF–
SYSREF+
Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)
tSU_SR
tH_SR
Figure 3. SYSREF± Setup and Hold Timing
Rev. 0 | Page 9 of 101
 

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