datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

AD9694 View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9694 Datasheet PDF : 101 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
AD9694
CONVERTER A
INPUT
ADC A
CONVERTER B
INPUT
ADC B
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
Data Sheet
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
0x05B2,
0x05B3)
SERDOUTAB0+
SERDOUTAB0–
SERDOUTAB1+
SERDOUTAB1–
SYSREF±
SYNCINAB±
SYNCINCD±
CONVERTER C
INPUT
ADC C
CONVERTER D
INPUT
ADC D
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
0x05B2,
0x05B3)
SERDOUTCD0+
SERDOUTCD0–
SERDOUTCD1+
SERDOUTCD–
Figure 81. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)
JESD204B LONG
TRANSPORT TEST
PATTERN
REG 0x0571[5]
JESD204B
INTERFACE TEST
PATTERNS
(REG 0x0573,
REG 0x0551 TO REG 0x0558)
JESD204B DATA
LINK LAYER TEST
PATTERNS
REG 0x0574[2:0]
ADC TEST PATTERNS
(REG 0x0550,
REG 0x0551 TO REG 0x0558)
MSB A13
A12
A11
A10
A9
ADC
A8
A7
A6
A5
A4
A3
A2
A1
LSB A0
C2
CONTROL BITS C1
C0
JESD204B SAMPLE
CONSTRUCTION
TAIL BITS
REG 0x0571[6]
TRANSPORT
LAYER
FRAME
CONSTRUCTION
SCRAMBLER
1 + x14 + x15
(OPTIONAL)
8-BIT/10-BIT
ENCODER
SERIALIZER
SERDOUT0±
SERDOUT1±
a b .... i j a b .... i j
MSB A13 A5
A12 A4
A11 A3
A10 A2
A9 A1
A8 A0
A7 C2
LSB A6 T
MSB S7 S7
S6 S6
S5 S5
S4 S4
S3 S3
S2 S2
S1 S1
LSB S0 S0
SYMBOL0
a bcd e f gh i j
a bcd e f gh i j
SYMBOL1
Figure 82. ADC Output Data Path Showing Data Framing
DATA LINK
LAYER
PHYSICAL
LAYER
PROCESSED
SAMPLES
FROM ADC
SAMPLE
FRAME
CONSTRUCTION CONSTRUCTION
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
CROSSBAR
MUX
SERIALIZER
Tx
OUTPUT
SYSREF±
SYNCINB±x
Figure 83. Data Flow
Rev. 0 | Page 50 of 101
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]