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AD9694-500EBZ View Datasheet(PDF) - Analog Devices

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AD9694-500EBZ Datasheet PDF : 101 Pages
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AD9694
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI
settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ)
range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
INPUT REFERRED NOISE
ANALOG INPUTS
Differential Input Voltage Range (Programmable)
Common-Mode Voltage (VCM)
Differential Input Capacitance1
Differential Input Resistance
Analog Input Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD1_SR
AVDD2
AVDD3
DVDD
DRVDD1
DRVDD2
SPIVDD
IAVDD1
IAVDD1_SR
IAVDD2
IAVDD3
IDVDD 2
IDRVDD11
IDRVDD21
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)2
Power-Down Dissipation
Standby3
Min
Typ
Max
14
Guaranteed
0
0
−5.0
+5.0
1.0
−0.7
±0.4
+0.7
−5.1
±1.0
+5.1
8
214
0.5
2.6
1.44
1.80
2.16
1.34
1.75
200
1.4
0.95
0.975
1.00
0.95
0.975
1.00
1.71
1.8
1.89
2.44
2.5
2.56
0.95
0.975
1.00
0.95
0.975
1.00
1.71
1.8
1.89
1.71
1.8
1.89
319
482
21
53
438
473
87
103
121
180
162
207
23
29
1
1.6
1.66
2.07
325
1.20
Unit
Bits
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
V
LSB rms
V p-p
V
pF
GHz
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
W
mW
W
1 All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.
2 Full bandwidth mode.
3 Standby mode is controlled by the SPI.
Rev. 0 | Page 4 of 101
 

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