AD9694-500EBZ View Datasheet(PDF) - Analog Devices
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AD9694-500EBZ Datasheet PDF : 101 Pages
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Data Sheet
GENERAL DESCRIPTION
The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital
converter (ADC). The device has an on-chip buffer and a
sample-and-hold circuit designed for low power, small size, and
ease of use. This device is designed for sampling wide bandwidth
analog signals of up to 1.4 GHz. The AD9694 is optimized for
wide input bandwidth, high sampling rate, excellent linearity,
and low power in a small package.
The quad ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The analog inputs and clock signals are differential inputs. Each
pair of ADC data outputs is internally connected to two DDCs
through a crossbar mux. Each DDC consists of up to five cascaded
signal processing stages: a 48-bit frequency translator, NCO,
and up to four half-band decimation filters.
In addition to the DDC blocks, the AD9694 has several
functions that simplify the automatic gain control (AGC)
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
AD9694
Users can configure each pair of intermediate frequency (IF)
receiver outputs onto either one or two lanes of Subclass 1
JESD204B-based high speed serialized outputs, depending on
the decimation ratio and the acceptable lane rate of the receiving
logic device. Multiple device synchronization is supported through
the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.
The AD9694 has flexible power-down options that allow significant
power savings when desired. All of these features can be pro-
grammed using the 1.8 V capable, 3-wire SPI.
The AD9694 is available in a Pb-free, 72-lead LFCSP and is
specified over the −40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or
international patents.
PRODUCT HIGHLIGHTS
1. Low power consumption per channel.
2. JESD204B lane rate support up to 15 Gbps.
3. Wide full power bandwidth supports IF sampling of signals
up to 1.4 GHz.
4. Buffered inputs ease filter design and implementation.
5. Four integrated wideband decimation filters and
numerically controlled oscillator (NCO) blocks supporting
multiband receivers.
6. Programmable fast overrange detection.
7. On-chip temperature diode for system thermal management.
Rev. 0 | Page 3 of 101
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