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ML145050-6P View Datasheet(PDF) - LANSDALE Semiconductor Inc.

Part Name
Description
View to exact match
ML145050-6P
LANSDALE
LANSDALE Semiconductor Inc. LANSDALE
ML145050-6P Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ML145050, ML145051
LANSDALE Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Figure
Symbol
Parameter
Guaranteed
Limit
Unit
1
f
Clock Frequency, SCLK
Note: Refer to twH, twL below
1
f
Clock Frequency, ADCLK
Note: Refer to twH, twL below
1
twH
Minimum Clock High Time
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
Minimum
Maximum
ADCLK
SCLK
0
Note 1
2.1
500
2.1
190
190
MHz
kHz
MHz
ns
1
twL
Minimum Clock Low Time
ADCLK
190
ns
SCLK
190
1, 7
tPLH, tPHL Maximum Propagation Delay, SCLK to Dout
1, 7
th
Minimum Hold Time, SCLK to Dout
2, 7
tPLZ, tPHZ Maximum Propagation Delay, CS to Dout High-Z
2, 7
tPZL, tPZH Maximum Propagation Delay, CS to Dout Driven
125
ns
10
ns
150
ns
ML145050 2 ADCLK cycles + 300 ns
ML145051
2.3
µs
3
3
4, 7, 8
5
tsu
Minimum Setup Time, Din to SCLK
th
Minimum Hold Time, SCLK to Din
td
Maximum Delay Time, EOC to Dout (MSB)
tsu
Minimum Setup Time, CS to SCLK
100
ns
0
ns
ML145051
100
ns
ML145050 2 ADCLK cycles + 425 ns
ML145051
2.425
µs
tCSd
Minimum Time Required Between 10th SCLK Falling
Edge ( 0.8 V) and CS to Allow a Conversion
ML145050
ML145051
44
Note 2
ADCLK
cycles
tCAs
Maximum Delay Between 10th SCLK Falling Edge
( 2 V) and CS to Abort a Conversion
ML145050
36
ADCLK
cycles
ML145051
9
µs
5
th
Minimum Hold Time, Last SCLK to CS
0
ns
6, 8
tPHL
Maximum Propagation Delay, 10th SCLK to EOC
ML145051
2.35
µs
1
tr, tf
Maximum Input Rise and Fall Times
SCLK
1
ms
ADCLK
250
ns
Din, CS
10
µs
1, 4, 6 – 8 tTLH, tTHL Maximum Output Transition Time, Any Output
300
ns
Cin
Maximum Input Capacitance
AN0 – AN10
55
pF
ADCLK, SCLK, CS, Din
15
Cout
Maximum Three-State Output Capacitance
Dout
15
pF
NOTES:
1. After the 10th SCLK falling edge (2 V), at least 1 SCLK rising edge (2 V) must occur within 38 ADCLKs (ML145050) or 18.5 µs
(ML145051).
2. On the ML145051, a CS edge may be received immediately after an active transition on the EOC pin.
Page 4 of 15
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