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HI-8581CJT-10 View Datasheet(PDF) - Holt Integrated Circuits

Part NameHI-8581CJT-10 Holt
Holt Integrated Circuits Holt
DescriptionARINC 429 Transmitter with Line Driver and Dual Receivers


HI-8581CJT-10 Datasheet PDF : 15 Pages
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PIN DESCRIPTION
HI-8581, HI-8589
SIGNAL
VCC
V+
V-
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
FUNCTION
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
TX/R
OUTPUT
PL1
PL2
TXA(OUT)
TXB(OUT)
ENTX
CWSTR
CLK
TX CLK
MR
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
DESCRIPTION
+5V ±5%
+9.5V to +10.5V
-9.5V to -10.5V
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Line driver output - A side
Line driver output - B side
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
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GENERAL DESCRIPTION
The HI-8581 and HI-8589 from Holt Integrated Circuits are silicon gate CMOS devices for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. Both devices provide two receivers, an independent transmitter and line driver capability in a single package. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The transmitter section provides the ARINC 429 communication protocol and the line driver circuits provide the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOS and TTL.
The HI-8581 has 37.5 ohms in series with each line driver output. The HI-8589 provides the option to bypass most of the internal output resistance so that external series resistance may be added for lighting protection and still match the 75 ohm characteristic impedance of the ARINC bus.

FEATURES
• ARINC specification 429 compliant
• Direct receiver and transmitter interface to ARINC bus in a single device
• 16-Bit parallel data bus
• Timing control 10 times the data rate
• Selectable data clocks
• Receiver error rejection per ARINC 429 standard
• Automatic transmitter data timing
• Parity functions
• Low power
• Self test mode
• Industrial & extended temperature ranges

 

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