EtronTech
1M x 16 SDRAM EM636165-XXI
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = -40~85°C) (Note: 5, 6, 7, 8)
Symbol
A.C. Parameter
TRC Row cycle time
(same bank)
tRCD RAS# to CAS# delay
(same bank)
TRP Precharge to refresh/row activate
command (same bank)
tRRD Row activate to row activate delay
(different banks)
tRAS Row activate to precharge time
(same bank)
tWR Write recovery time
TCK1
TCK2
TCK3
TCH
TCL
TAC1
tAC2
tAC3
tCCD
tOH
tLZ
tHZ
tIS
tIH
tPDE
tREF
CL* = 1
Clock cycle time
CL* = 2
CL* = 3
Clock high time
Clock low time
Access time from CLK
CL* = 1
(positive edge)
CL* = 2
CL* = 3
CAS# to CAS# Delay time
Data output hold time
Data output low impedance
Data output high impedance
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
PowerDown Exit set-up time
Refresh time
* CL is CAS# Latency.
-6I(G)/7I(G)/8I(G)/10I(G)
Min.
Max.
54/63/72/90
16/16/16/30
16/16/16/30
12/14/16/20
36/42/48/60
100,000
1
-20/20/20/30
-7.5/8/8/15
6/7/8/10
2/2.5/3/3.5
2/2.5/3/3.5
1
2/2/2/3
1/1/2/2
2/2/2.5/3
1
6/7/8/10
-8/13/18/27
-6/6.5/7/12
5/5.5/6.5/7.5
4/5/6/8
64
Unit Note
9
9
ns 9
9
Cycle
10
ns 11
11
11
Cycle
10
8
ns 11
11
ms
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
Preliminary
19
Rev. 1.1 Apr. 2005