EtronTech
1M x 16 SDRAM
EM636165
Figure 4. Power on Sequene and Auto Refresh (CBR)
CLK
CKE
CS#
RAS#
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
High level
is reauired
Minimum of 2 Refresh Cycles are required
CAS#
WE#
A11
A10
A0-A9
Address Key
DQM
tRP
tRC
DQ Hi-Z
PrechargeALL
1st AutoRefresh (*)
Command
Command
Inputs must be
stable for 200 ยตs
Mode Register
Set Command
(*)
2nd Auto Refresh
Command
Note (*) : The Auto Refresh command can be issued before or after Mode Register Set command
Any
Command
Preliminary
25
Rev. 2.7 Mar. 2006