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CX28HC256FMB-15 View Datasheet(PDF) - Rochester Electronics

Part Name
Description
View to exact match
CX28HC256FMB-15
ROCHESTER
Rochester Electronics ROCHESTER
CX28HC256FMB-15 Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pinouts
X28HC256
(28 LD CERDIP, FLATPACK, PDIP, SOIC)
TOP VIEW
A14 1
28 VCC
A12
2
27 WE
A7 3
26 A13
A6 4
25 A8
A5 5
24 A9
A4 6
23 A11
A3
7
22
X28HC256
OE
A2 8
21 A10
A1 9
20 CE
A0 10
19 I/O7
I/O0 11
18 I/O6
I/O1 12
17 I/O5
I/O2 13
16 I/O4
VSS 14
15 I/O3
X28HC256
X28HC256
(32 LD PLCC, LCC)
TOP VIEW
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
A2 9
X28HC256
26 NC
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
Pin Descriptions
Addresses (A0 to A14)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O0 to I/O7)
Data is written to or read from the X28HC256 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
X28HC256
(28 LD PGA)
BOTTOM VIEW
I/O1 I/O2 I/O3 I/O5 I/O6
12 13 15 17 18
I/O0 A0 VSS I/O4 I/O7
11 10 14 16 19
A1 A2
98
CE A10
20 21
X28HC256
A3 A4
OE A11
76
22 23
5A5 2A12 28VCC 24A9 25A8
A6
4
A7
3
1 A14
WE
27
A13
26
4
FN8108.2
May 7, 2007
 

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