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HN58X2408FPIE View Datasheet(PDF) - Renesas Electronics

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Description
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HN58X2408FPIE Datasheet PDF : 22 Pages
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HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to VCC or VSS. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated. As for 8k to 16k EEPROM, whole or some device address pins don't need to be
fixed since device address code provided from the SDA pin is used as memory address signal.
Pin Connections for A0 to A2
Pin connection
Max connect
Memory size number
A2
A1
A0
8k bit
2
VCC/VSS* ×*2
×
1
Notes
Use A0, A1 for memory address a8 and a9
16k bit
1
×
×
×
Use A0, A1, A2 for memory address a8, a9 and
a10
32k bit
8
VCC/VSS VCC/VSS VCC/VSS
64k bit
8
VCC/VSS VCC/VSS VCC/VSS
Notes: 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS.
2. × = Don’t care (Open is also approval.)
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
WP pin
status
VIH
VIL
Write protect area
8k bit
16k bit
Upper 1/2 (4k bit)
Upper 1/2 (8k bit)
Normal read/write operation
32k bit
Upper 1/4 (8k bit)
64k bit
Upper 1/4 (16k bit)
Rev.5.00, Jan.14.2005, page 8 of 20
 

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