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SPT7720 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
SPT7720
Fairchild
Fairchild Semiconductor Fairchild
SPT7720 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Figure 3 – Typical Interface Circuit
+A5
Single
Mode
Data
Sync
Dual
Mode
Clock In
VIN
(1 VP-P)
0.1 µF
0.1 µF
1KW
0.1 µF
(+2.5 V typ)
VREFOUT
VREFIN
AIN
SPT7720
AIN
Port A
DA0–7
DB0–7
Port B
Interfacing
Logics
Notes:
1) FB = Ferrite bead. It must placed as close to the DUT as possible.
2) All 0.01 microfarad capacitors are surface mount caps. They must be
placed as close to the respective pin as possible.
.01 µF (9x)
FB
+
10 µF
+A5
+D5
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 3 shows the typical
interface requirements when using the SPT7720 in nor-
mal circuit operation. The following sections provide de-
scriptions of the major functions and outline performance
criteria to consider for achieving the optimal device
performance.
ANALOG INPUT
The input of the SPT7720 can be configured in various
ways depending on whether a single-ended or differential
input is desired.
The AC-coupled input is most conveniently implemented
using a transformer with a center-tapped secondary wind-
ing. The center tap is connected to the VCM pin as shown
in figure 3. To obtain low distortion, it is important that the
selected transformer does not exhibit core saturation at
the full-scale voltage. Proper termination of the input is im-
portant for input signal purity. A small capacitor across the
input attenuates kickback noise from the internal track-
and-hold.
Figure 4 illustrates a solution (based on operational ampli-
fiers) that can be used if a DC-coupled single-ended input
is desired. It is very important to select op amps with a
high open-loop gain, a bandwidth high enough so as not to
impair the performance of the ADC, low THD, and high
SNR.
Figure 4 – DC-Coupled Single-Ended to Differential
Conversion (power supplies and bypassing
are not shown)
R3
VCM
R3
–
+
Input
Voltage
(±0.5 V)
(R3)/2
R
R2
R2
R
–
51 W
+
15 pF
ADC
VIN+
VIN–
51 W
+
R
–
R
R
51 W
INPUT PROTECTION
All I/O pads are protected with an on-chip protection
circuit. This circuit provides ESD robustness and prevents
latchup under severe discharge conditions without
degrading analog transmission times.
POWER SUPPLIES AND GROUNDING
The SPT7720 is operated from a single power supply in
the range of 4.75 to 5.25 volts. Normal operation is sug-
gested to be 5.0 volts. All power supply pins should be by-
passed as close to the package as possible.
SPT7720
7
5/9/01
 

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