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MC68HC908RF2 View Datasheet(PDF) - Motorola => Freescale

Part NameDescriptionManufacturer
MC68HC908RF2 high-performance M68HC08 Family of 8-bit microcontroller units Motorola
Motorola => Freescale Motorola
MC68HC908RF2 Datasheet PDF : 254 Pages
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FLASH 2TS Memory
4.3 Functional Description
The FLASH 2TS memory is appropriately named to describe its
2-transistor source-select bit cell. The FLASH 2TS memory is an array
of 2031 bytes with an additional 14 bytes of user vectors and one byte
for block protection. An erased bit reads as a logic 0 and a programmed
bit reads as a logic 1.
The address ranges for the user memory, control register, and vectors
are:
$7800$7FEE, user space
$7FEF, reserved optional ICG trim value, see 8.8.3 ICG Trim
Register
$FFF0, block protect register
$FE08, FLASH 2TS control register
$FFF2$FFFF, these locations are reserved for user-defined
interrupt and reset vectors
This list is the row architecture for the user space array:
$7800$7807 (Row 0)
$7808$780F (Row 1)
$7810$7817 (Row 2)
$7818$781F (Row 3)
$7820$7827 (Row 4)
--------------------------
$7FE8$7FEF (Row 253)
Program and erase operations are facilitated through control bits in a
memory mapped register. Details for these operations appear later in
this section. Memory in the FLASH 2TS array is organized into pages
within rows. For the 2-Kbyte array on the MC68HC908RF2, the page
size is one byte. There are eight pages (or eight bytes) per row.
Programming operations are performed on a page basis, one byte at a
time. Erase operations are performed on a block basis. The minimum
Advance Information
46
FLASH 2TS Memory
MC68HC908RF2 Rev. 1
MOTOROLA
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