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ADC0808MFK View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADC0808MFK CMOS ANALOG-TO-DIGITAL CONVERTER WITH 8-CHANNEL ΜULTIPLEXER TI
Texas Instruments TI
ADC0808MFK Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
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ADC0808M
CMOS ANALOGĆTOĆDIGITAL CONVERTER
WITH 8ĆCHANNEL MULTIPLEXER
SGLS005A − D2642, NOVEMBER 1986 − REVISED MAY 1988
electrical characteristics over recommended operating free-air temperature range, VCC = 4.5 V to
5.5 V (unless otherwise noted)
total device
VOH
VOL
IOZ
II
IIL
ICC
Ci
Co
PARAMETER
High-level output voltage
Low-level output voltage
Data outputs
End of conversion
Off-state (high-impedance-state)
output current
Control input current at maiximum input voltage
Low-level control input current
Supply current
Input capacitance, control inputs
Output capacitance, data outputs
Resistance from REF+ to REF −
TEST CONDITIONS
IO = −360 µA
IO = 1.6 mA
IO = 1.2 mA
VO = VCC
VO = 0
VI = 15 V
VI = 0
fclock = 640 kHz
TA = 25°C
TA = 25°C
MIN
TYP†
VCC −0.4
0.3
10
10
1000
MAX
0.45
0.45
3
−3
1
−1
3
UNIT
V
V
µA
µA
µA
mA
pF
pF
k
analog multiplexer
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
Ion Channel on-state current (see Note 3)
VI = VCC,
VI = 0,
fclock = 640 kHz
fclock = 640 kHz
2
µA
−2
Ioff Channel off-state current
VCC = 5 V,
TA = 25°C
VCC = 5 V
VI = 5 V
VI = 0
VI = 5 V
VI = 0
10 200
nA
−10 −200
1
µA
−1
Typical values are at VCC = 5 V and TA = 25°C.
NOTE 3: Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock frequency.
timing characteristics, VCC = Vref+ = 5 V, Vref− = 0 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
fclock
Clock frequency
10 640
tconv
Conversion time
See Notes 4 and 5 and Figure 1
90 100
tenH
Enable time, high
See Figure 1
150
tenL
Enable time, low
See FIgure 1
90
tdis
Output disable time
See Figure 1
200
tw(s)
Pulse duration, START
200
tw(ALE) Pulse duration, ALE
200
tsu
Setup time, ADDRESS
50
th
Hold time, ADDRESS
50
td(EOC) Delay time, EOC
See Notes 4 and 6 and Figure 1
0
NOTES: 4. Refer to the operating sequence diagram
5. For clock frequencies other than 640 kHz, tconv is 57 clock cycles minimum and 74 clock cycles maximum.
6. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock cycles plus 2 µs.
1280
116
360
25
405
14.5
UNIT
kHz
µs
ns
ns
ns
ns
ns
ns
ns
µs
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
5
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