HN58X25128 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

View to exact match

HN58X25128

Serial Peripheral Interface 128k EEPROM (16-kword × 8-bit)/256k EEPROM (32-kword × 8-bit)

Renesas Electronics 

HN58X25128FPIAG/HN58X25256FPIAG

Functional Description

Status Register

The following figure shows the Status Register Format. The Status Register contains a number of status and control

bits that can be read or set (as appropriate) by specific instructions.

Status Register Format

b7

b0

SRWD 0

0

0

BP1 BP0 WEL WIP

Status Register Write Disable

Block Protect Bits

Write Enable Latch Bits

Write In Progress Bits

WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register

cycle.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software

protected against Write instructions.

SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal.

The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.

Instructions

Each instruction starts with a single-byte code, as summarized in the following table. If an invalid instruction is sent

(one not contained in the following table), the device automatically deselects itself.

Instruction Set

WREN

WRDI

RDSR

WRSR

READ

WRITE

Instruction

Description

Write Enable

Write Disable

Read Status Register

Write Status Register

Read from Memory Array

Write to Memory Array

Instruction Format

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

R10DS0225EJ0200 Rev.2.00

Nov 29, 2013

Page 9 of 19

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