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MT4C4001JC-8/883C View Datasheet(PDF) - Micross Components

Part Name
Description
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MT4C4001JC-8/883C
MICROSS
Micross Components MICROSS
MT4C4001JC-8/883C Datasheet PDF : 21 Pages
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DRAM
MT4C4001J
NOTES:
1. All voltages referenced to Vss.
2. This parameter is sampled, not 100% tested. Capacitance is
measured with Vcc=5V, f=1 MHz at less than 50mVrms, TA =
25°C ±3°C, Vbias = 2.4V applied to each input and output
individually with remaining inputs and outputs open.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates. Speci-
ed values are obtained with minimum cycle time and the
output open.
5. Enables on-chip refresh and address counters.
6. The minimum specications are used only to indicate cycle
time at which proper operation over the full temperature range
(-55°C < TA < 125°C) is assured.
7. An initial pause of 100μs is required after power-up fol-
lowed by eight RAS\ refresh cycles (RAS\-ONLY or CBR with
WE\ HIGH) before proper device operation is assured. The
eight RAS\ cycle wake-up should be repeated any time the
16ms refresh requirement is exceeded.
8. AC characteristics assume tT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
suring timing of input signals. Transition times are
mea-
mea-
sured between VIH and VIL (or between VIL and VIH).
10. In addition to meeting the transition rate specication, all
input signals must transit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
11. If CAS\ = VIH, data outputs (DQs) are High-Z.
12. If CAS\ = VIL, data outputs (DQs) may contain data from
the last valid READ cycle.
13. Measured with a load equivalent to two TTL gates and
100pF.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the
maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
15. Assumes that tRCD > tRCD (MAX)
16. If CAS\ is LOW at the falling edge of RAS\, DQs will be
maintained from the previous cycle. To initiate a new cycle
and clear the data out buffer, CAS\ must be pulsed HIGH for
tCPN.
17. Operation within the tRCD (MAX) limit ensures that tRAC
(MAX) can be met. tRCD (MAX) is specied as a reference
point only; if tRCD is greater than the specied tRCD (MAX) limit,
then access time is controlled exclusively by tCAC.
18. Operation within the tRAD (MAX) limit ensures that tRCD
(MAX) can be met. tRAD (MAX) is specied as a reference
point only; if tRAD is greater than the specied tRAD (MAX)
limit, then access time is controlled exclusively by tAA.
19. Either tRCH or tRRH must be satised for a READ cycle.
20. tOFF (MAX) denes the time at which the output achieves the
open circuit conditions and is not referenced to VOH or VOL.
21. tWCS, tRWD, tAWD, and tCWD are not restrictive operating pa-
rameters. tWCS applies to EARLY-WRITE cycles. tRWD, tAWD,
and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS
> tWCS (MIN), the cycle is an EARLY-WRITE cycles and the
data output will remain an open circuit throughout the entire
cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and tCWD >
tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the
data output will contain data read from the selected cell. If
neither of the above conditions is met, the state of the data out
is indeterminate. OE\ held HIGH and WE\ taken LOW after
CAS\ goes LOW results in a LATE-WRITE (OE\ controlled)
cycle. tWCS, tRWD, tCWD, and tAWD are not
LATE-WRITE cycle.
applicable in a
22. These parameters are referenced to CAS\ leading edge
in EARLY-WRITE cycle and WE\ leading edge in LATE-
WRITE cycles and WE\ leading edge in LATE-WRITE or
READ-MODIFY-WRITE cycle.
23. If OE\ is tied permanently LOW, LATE-WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE\=LOW and OE\=HIGH.
25. tWTS and tWTH are setup and hold specications for the WE\
pin being held LOW to enable the JEDEC test mode (with CBR
timing constraints). These two parameters are the inverts
of tWRP and tWRH in the CBR REFRESH cycle.
26. LATE-WRITE and READ-MODIFY-WRITE cycles must
have both tOD and tOEH met (OE\ HIGH during WRITE cycle)
in order to ensure that the output buffers will be open during
the WRITE cycle. The DQs will provide the previously read
data if CAS\ remains LOW and OE\ is taken back LOW after
tOEH is met. If CAS\ goes HIGH prior to OE\ going back LOW,
the DQs will remain open.
27. The DQs open during READ cycles once tOD or tOFF oc-
cur. If CAS\ goes HIGH rst, OE\ becomes a “don’t care.”
If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t
care;” and the DQs will provide the previously read data if OE\
is taken back LOW (while CAS\ remains LOW).
28. JEDEC test mode only.
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specications without notice.
7
 

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