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MT4C4001JC-12 View Datasheet(PDF) - Micross Components

Part Name
Description
View to exact match
MT4C4001JC-12
MICROSS
Micross Components MICROSS
MT4C4001JC-12 Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DRAM
MT4C4001J
1 MEG x 4 DRAM
Fast Page Mode DRAM
PIN ASSIGNMENT
(Top View)
20-Pin DIP (C, CN)
20-Pin SOJ (ECJ,ECJA),
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR),
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
• Timing
70ns access
MARKING
-7
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
1 20 Vss
2 19 DQ4
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
3 18 DQ3
4
17 CAS\
DQ1
1
5 16 OE\
DQ2 2
6 15 A8
WE\ 3
RAS\ 4
7 14 A7
A9 5
26 Vss
25 DQ4
24 DQ3
23 CAS\
22 OE\
8 13 A6
9 12 A5
A0 9
10 11 A4
A1 10
A2 11
A3 12
20-Pin DIP (CZ) Vcc 13
18 A8
17 A7
16 A6
15 A5
14 A4
OE\ 1
DQ3 3
Vss 5
DQ2 7
RAS\ 9
A0 11
A2 13
Vcc 15
A5 17
A7 19
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
80ns access
-8
100ns access
-10
120ns access
-12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state memory
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC*
Ceramic ZIP
Ceramic SOJ
Ceramic SOJ w/ Cu J-lead
Ceramic Gull Wing
CN
C
ECN
CZ
ECJ
ECJA
ECG
No. 103
No. 104
No. 202
No. 400
No. 504
No. 504A
No. 600
containing 4,194,304 bits organized in a x4 conguration. Dur-
ing READ or WRITE cycles each bit is uniquely addressed
through the 20 address bits which are entered 10 bits (A0-
A9) at a time. RAS\ is used to latch the rst 10 bits and CAS\
the later 10 bits. A READ or WRITE cycle is selected with
the WE\ input. A logic HIGH on WE\ dictates READ mode
while a logic LOW on WE\ dictates WRITE mode. During a
WRITE cycle, data-in (D) is latched by the falling edge of WE\
or CAS\, whichever occurs last. If WE\ goes LOW prior to
CAS\ going LOW, the output pin(s) remain open (High-Z) until
*NOTE: If solder-dip and lead-attach is desired on LCC pack- the next CAS\ cycle. If WE\ goes LOW after data reaches the
ages, lead-attach must be done prior to the solder-dip opera- output pin(s), Qs are activated and retain the selected cell data
tion.
as long as CAS\ remains low (regardless of WE\ or RAS\).
This LATE WE\ pulse results in a READ-WRITE cycle. The
For more products and information
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four data inputs and four data outputs are routed through four
pins using common I/O and pin direction is controlled by WE\
and OE\. FAST-PAGE-MODE operations allow faster data
operations (READ, WRITE, or READ-MODIFY-WRITE)
within a row address (A0-A9) dened page boundary. The
FAST PAGE MODE
(continued)
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specications without notice.
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