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CXA1372BS View Datasheet(PDF) - Sony Semiconductor

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Description
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CXA1372BS Datasheet PDF : 32 Pages
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CXA1372BQ/BS
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the
rotation cycle envelope fluctuation.
RFO
39
RFI
× 2.2
G
MIRROR AMP
MIRROR HOLD AMP
PEAK &
H
BOTTOM
×1
HOLD
I
J
K
0.033µ
38
CP
20k
MIRROR
COMPARATOR DGND
29
MIRR
RFO
0V
G
(RFI)
0V
H
(PEAK HOLD)
0V
I
(BOTTOM HOLD)
0V
J
K
(MIRROR HOLD)
MIRR
H
L
Through differential amplification of the peak and bottom hold signals H and I, mirror output can be obtained by
comparing an envelope signal J (demodulated to DC) to signal K for Which peak holding at a level 2/3 that of
the maximum was performed with a large time constant. In other words, mirror output is low for tracks on the
disc and high for the area between tracks (the MIRR areas). In addition, a high signal is output when a defect
is detected. The mirror hold time constant must be sufficiently large in comparison with the traverse signal.
– 17 –
 

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