|TD351I||Advanced IGBT/MOSFET driver|
|TD351I Datasheet PDF : 19 Pages |
Ta is approximately given by (see Figure 5):
Ta(µs) = 0.7 ⋅ Rd(kΩ) ⋅ Cd(nF)
The turn-off delay (Ta) is also used to delay the input signal to prevent distortion of input
The two-level turn-off sequence can be disabled by connecting the LVOFF pin to VH and
connecting the CD pin to VREF with a 4.7 kΩ resistor.
Minimum input ON-time
Input signals with ON-time smaller than Ta are ignored.
ON-time signals larger than Ta+2.Rdel.Cd (Rdel is the internal discharge switch resistance,
Cd is the external timing capacitor) are transmitted to the output stage after the Ta delay, with
minimum width distortion (∆Tw=Twout-Twin).
For ON-time input signals close to Ta (between Ta and Ta+2.Rdel.Cd), the two-level duration
is slightly reduced and the total output width can be smaller than the input width (see
The output stage is able to sink/source 1.7 A/1.3 A (typical) at 25 °C and 1.0 A/0.75 A min.
over the full temperature range. This current capability is specified near the usual IGBT
Undervoltage detection protects the application in the event of a low VH supply voltage
(during startup or a fault situation). During undervoltage, the OUT pin is driven low (active
pull-down for VH>2V, and passive pull-down for VH<2V).
Doc ID 10977 Rev 2
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