W631GG6KB View Datasheet(PDF) - Winbond

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Description

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W631GG6KB

1G bits DDR3 SDRAM, organized as 8,388,608 words x 8 banks x 16 bits.

Winbond 

W631GG6KB

7.3.3 Mode Register MR2

The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance,

and CAS write latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#,

high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the

Figure 7 below.

BA2 BA1 BA0 A12 A11 A10

A9 A8

A7

A6

A5

A4

A3

A2

A1

A0

Address Field

0*1

1

0

0*1

Rtt_WR

0*1 SRT ASR

CWL

PASR

Mode Register 2

BA1 BA0

0

0

0

1

1

0

1

1

MR Select

MR0

MR1

MR2

MR3

A6 Auto Self Refresh (ASR)

0 Manual SR Reference (SRT)

1

ASR enable

A7 Self Refresh Temperature (SRT) Range

0

Normal operating temperature range

1

Extended operating temperature range

A10 A9

Rtt_WR*2

Dynamic ODT off

0

0 (Write does not affect Rtt value)

0

1

RZQ/4

1

0

RZQ/2

1

1

Reserved

A2 A1 A0

Partial Array Self Refresh for 8 Banks

0

0

0

Full array

0

0

1

Half Array (BA[2:0]=000,001,010 & 011)

0

1

0

Quarter Array (BA[2:0]=000 & 001)

0

1

1

1/8th Array (BA[2:0]=000)

1

0

0 3/4 Array (BA[2:0]=010,011,100,101,110 & 111)

1

0

1

Half Array (BA[2:0]=100,101,110 & 111)

1

1

0

Quarter Array (BA[2:0]=110 & 111)

1

1

1

1/8th Array (BA[2:0]=111)

A5 A4 A3 CAS write Latency (CWL)

0

0

0 5 (tCK(avg) ≥ 2.5nS)

0

0

1 6 (2.5nS > tCK(avg) ≥ 1.875nS)

0

1

0 7 (1.875nS > tCK(avg) ≥ 1.5nS)

0

1

1 8 (1.5nS > tCK(avg) ≥ 1.25nS)

1

0

0 9 (1.25nS > tCK(avg) ≥ 1.07nS)

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

Notes:

1. BA2, A8, A11~A12 are reserved for future use and must be programmed to 0 during MRS.

2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not

available.

Figure 7 – MR2 Definition

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Publication Release Date: Feb. 27, 2013

Revision A04

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