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ISL12022MA View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12022MA Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving Intersil
Intersil Intersil
ISL12022MA Datasheet PDF : 29 Pages
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ISL12022MA
DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 7) (Note 8) (Note 7) UNITS NOTES
Temp Temperature Sensor Accuracy
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL Output Low Voltage
VDD = VBAT = 3.3V
VDD = 5V, IOL = 3mA
VDD = 2.7V, IOL = 1mA
±2
°C
13
0.4
V
0.4
V
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 7) (Note 8) (Note 7) UNITS NOTES
VDDSR-
VDD Negative Slew Rate
10
V/ms
12
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 8) (Note 7) UNITS NOTES
VIL SDA and SCL Input
Buffer LOW Voltage
-0.3
0.3 x VDD V
VIH SDA and SCL Input
Buffer HIGH Voltage
0.7 x VDD
VDD + 0.3 V
Hysteresis SDA and SCL Input
Buffer Hysteresis
0.05 x VDD
V 13, 14
VOL SDA Output Buffer
VDD = 5V, IOL = 3mA
LOW Voltage, Sinking
3mA
0
0.02
0.4
V
CPIN
fSCL
tIN
SDA and SCL Pin
Capacitance
SCL Frequency
Pulse Width
Suppression Time at
SDA and SCL Inputs
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
Any pulse narrower than the max
spec is suppressed.
10
pF 13, 14
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SCL falling edge crossing 30% of
SDA Output Data Valid VDD, until SDA exits the 30% to
70% of VDD window.
Time the Bus Must be SDA crossing 70% of VDD during a
Free Before the Start of STOP condition, to SDA crossing
a New Transmission
70% of VDD during the following
START condition.
1300
900
ns
ns
tLOW Clock LOW Time
Measured at the 30% of VDD
1300
ns
crossing.
tHIGH Clock HIGH Time
Measured at the 70% of VDD
600
ns
crossing.
tSU:STA START Condition Setup SCL rising edge to SDA falling edge.
600
ns
Time
Both crossing 70% of VDD.
tHD:STA START Condition Hold From SDA falling edge crossing
600
ns
Time
30% of VDD to SCL falling edge
crossing 70% of VDD.
6
FN7575.1
July 9, 2010
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