datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

ISL12022MIBZ View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12022MIBZ Real Time Clock with Embedded Crystal, ±5ppm Accuracy Intersil
Intersil Intersil
ISL12022MIBZ Datasheet PDF : 27 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ISL12022M
VB85Tp2
0
0
0
0
1
1
1
TABLE 8. VB85T ALARM LEVEL
VB85Tp1
VB85Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0
0
2.125
0
1
2.295
1
0
2.550
1
1
2.805
0
0
3.060
0
1
4.250
1
0
4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>)
Three bits select the second alarm (75% of Nominal VBAT)
level for the battery voltage monitor. There are total of 7 levels
that could be selected for the second alarm. Any of the of levels
could be selected as the second alarm with no reference as to
nominal Battery voltage level. See Table 9.
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
(VB75TP <2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0
0
0
1.875
0
0
1
2.025
0
1
0
2.250
0
1
1
2.475
1
0
0
2.700
1
0
1
3.750
1
1
0
4.125
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT) and
Analog Trimming (AT) methods are available. The digital
trimming uses clock pulse skipping and insertion for
frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with combined
digital and analog trimming.
Initial values for the ITR0 register are preset internally and
recalled to RAM registers on power-up. These values are
pre-set in device production and are READ-ONLY. They
cannot be overwritten by the user. If an application
requires adjustment of the IATR bits outside the preset
values, the user should contact Intersil.
AGING AND INITIAL TRIM DIGITAL TRIMMING BITS
(IDTR0<1:0>)
These bits allow ±30.5ppm initial trimming range for the
crystal frequency. This is meant to be a coarse adjustment if
the range needed is outside that of the IATR control. See
Table 10. The IDTR0 register should only be changed while
the TSE (Temp Sense Enable) bit is “0”.
The ISL12022M has a preset Initial Digital Trimming value
corresponding to the crystal in the module. This value is
recalled on initial power-up and is READ-ONLY. It cannot
be overwritten by the user.
TABLE 10. IDTR0 TRIMMING RANGE
IDTR01
IDTR00
TRIMMING RANGE
0
0
Default/Disabled
0
1
+30.5ppm
1
0
0ppm
1
1
-30.5ppm
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0<5:0>)
The Initial Analog Trimming Register allows +32ppm to
-31ppm adjustment in 1ppm/bit increments. This enables
fine frequency adjustment for trimming initial crystal
accuracy error or to correct for aging drift.
The ISL12022M has a preset Initial Analog Trimming value
corresponding to the crystal in the module. This value is
recalled on initial power-up, is preset in device production
and is READ-ONLY. It cannot be overwritten by the user.
TABLE 11. INITIAL AT AND DT SETTING REGISTER
ADDR 7
6
5
4
3
2
1
0
0Bh IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
TABLE 12. IATRO TRIMMING RANGE
TRIMMING
IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE
0
0
0
0
0
0
+32
0
0
0
0
0
1
+31
0
0
0
0
1
0
+30
0
0
0
0
1
1
+29
0
0
0
1
0
0
+28
0
0
0
1
0
1
+27
0
0
0
1
1
0
+26
0
0
0
1
1
1
+25
0
0
1
0
0
0
+24
0
0
1
0
0
1
+23
0
0
1
0
1
0
+22
0
0
1
0
1
1
+21
0
0
1
1
0
0
+20
0
0
1
1
0
1
+19
0
0
1
1
1
0
+18
0
0
1
1
1
1
+17
0
1
0
0
0
0
+16
0
1
0
0
0
1
+15
0
1
0
0
1
0
+14
0
1
0
0
1
1
+13
0
1
0
1
0
0
+12
0
1
0
1
0
1
+11
16
FN6668.5
July 10, 2009
Direct download click here
 

Share Link : Intersil
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]