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ISL12022MIBZ View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12022MIBZ Real Time Clock with Embedded Crystal, ±5ppm Accuracy Intersil
Intersil Intersil
ISL12022MIBZ Datasheet PDF : 27 Pages
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ISL12022M
brownout levels are selected by three bits: VDD Trip2, VDD
Trip1 and VDD Trip0 in PWR_ VDD registers. The LVDD
detection is only enabled in VDD mode and the detection
happens in real time. The LVDD bit is set whenever the VDD
has dropped below the pre-selected trip level, and self clears
whenever the VDD is above the pre-selected trip level.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
In Normal Mode (VDD), this bit indicates when the battery
level has dropped below the pre-selected trip levels. The trip
points are selected by three bits: VB85Tp2, VB85Tp1 and
VB85Tp0 in the PWR_VBAT registers. The LBAT85
detection happens automatically once every minute when
seconds register reaches 59. The detection can also be
manually triggered by setting the TSE bit in BETA register to
“1”. The LBAT85 bit is set when the VBAT has dropped below
the pre-selected trip level, and will self clear when the VBAT
is above the pre-selected trip level at the next detection
cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has
entered into battery mode by polling once every 10 minutes.
The LBAT85 detection happens automatically once when the
minute register reaches x9h or x0h minutes.
Example - When the LBAT85 is Set To “1” In Battery Mode:
The minute the register changes to 19h when the device is in
battery mode, the LBAT85 is set to “1” the next time the
device switches back to Normal Mode.
Example - When the LBAT85 Remains at “0” In Battery
Mode:
If the device enters into battery mode after the minute
register reaches 20h and switches back to Normal Mode
before the minute register reaches 29h, then the LBAT85 bit
will remain at “0” the next time the device switches back to
Normal Mode.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
In Normal Mode (VDD), this bit indicates when the battery
level has dropped below the pre-selected trip levels. The trip
points are selected by three bits: VB75Tp2, VB75Tp1 and
VB75Tp0 in the PWR_VBAT registers. The LBAT75
detection happens automatically once every minute when
seconds register reaches 59. The detection can also be
manually triggered by setting the TSE bit in BETA register to
“1”. The LBAT75 bit is set when the VBAT has dropped below
the pre-selected trip level, and will self clear when the VBAT
is above the pre-selected trip level at the next detection
cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has
entered into battery mode by polling once every 10 minutes.
The LBAT85 detection happens automatically once when the
minute register reaches x9h or x0h minutes.
Example - When the LBAT75 is Set to “1” in Battery Mode:
The minute register changes to 30h when the device is in
battery mode, the LBAT75 is set to “1” the next time the
device switches back to Normal Mode.
Example - When the LBAT75 Remains at “0” in Battery
Mode:
If the device enters into battery mode after the minute register
reaches 49h and switches back to Normal Mode before
minute register reaches 50h, then the LBAT75 bit will remain
at “0” the next time the device switches back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12022M internally) when
the device powers up after having lost all power (defined as
VDD = 0V and VBAT = 0V). The bit is set regardless of
whether VDD or VBAT is applied first. The loss of only one of
the supplies does not set the RTCF bit to “1”. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is sufficient).
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR 7
6
5
4
3210
08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a valid
read of the respective status register (with a valid STOP
condition). When the ARST is cleared to “0”, the user must
manually reset the ALM, LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/FOUT pin when the RTC is
triggered by the alarm, as defined by the alarm registers
(0Ch to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/FOUT pin will be
set low until the ALM status bit is cleared to “0”.
14
FN6668.5
July 10, 2009
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