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24LC01 View Datasheet(PDF) - Holtek Semiconductor

Part NameDescriptionManufacturer
24LC01 1K/2K 2-Wire CMOS Serial EEPROM Holtek
Holtek Semiconductor Holtek
24LC01 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
HT24LC01/02
The 8th bit of device address is the read/write
operation select bit. A read operation is initi-
ated if this bit is high and a write operation is
initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the
chip will return to a standby state.
Write operations
Byte write
A write operation requires an 8-bit data word
address following the device address word
and acknowledgment. Upon receipt of this ad-
dress, the EEPROM will again respond with a
zero and then clock in the first 8-bit data
word. After receiving the 8-bit data word, the
EEPROM will output a zero and the address-
ing device, such as a microcontroller, must
terminate the write sequence with a stop con-
dition. At this time the EEPROM enters an
internally-timed write cycle to the non-vola-
tile memory. All inputs are disabled during
this write cycle and EEPROM will not re-
spond until the write is completed (refer to
Byte write timing).
Page write
The 1K/2K EEPROM is capable of an 8-byte
page write.
A page write is initiated the same as byte
write, but the microcontroller does not send a
stop condition after the first data word is
clocked in. Instead, after the EEPROM ac-
knowledges the receipt of the first data word,
the microcontroller can transmit up to seven
more data words. The EEPROM will respond
with a zero after each data word received. The
microcontroller must terminate the page
write sequence with a stop condition.
The data word address lower three (1K/2K)
bits are internally incremented following the
receipt of each data word. The higher data
word address bits are not incremented, re-
taining the memory page row location (refer
to Page write timing).
Acknowledge polling
Since the device will not acknowledge during
a write cycle, this can be used to determine
when the cycle is complete (this feature can be
used to maximize bus throughput). Once the
stop condition for a write command has been
issued from the master, the device initiates
the internally timed write cycle. ACK polling
can be initiated immediately. This involves
the master sending a start condition followed
by the control byte for a write command
(R/W=0). If the device is still busy with the
5
6th May ’99
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