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FAN302HLMY_F117 View Datasheet(PDF) - Fairchild Semiconductor

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FAN302HLMY_F117 Datasheet PDF : 18 Pages
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Operational Description
Basic Control Principle
Figure 24 shows the internal PWM control circuit. The
constant voltage (CV) regulation is implemented in the
same way as the conventional isolated power supply,
where the output voltage is sensed using a voltage
divider and compared with the internal 2.5V reference of
a shunt regulator (KA431) to generate a compensation
signal. The compensation signal is transferred to the
primary side using an opto-coupler and scaled down
through attenuator Av, generating the VEA.V signal. Then
the error signal VEA.V is applied to the PWM comparator
(PWM.V) to determine the duty cycle.
Meanwhile, the CC regulation is implemented internally
without directly sensing the output current. The output
current estimator reconstructs output current information
(VCCR) using the transformer primary-side current and
diode current discharge time. Then VCCR is compared
with a reference voltage (2.5V) by an internal error
amplifier, generating the VEA.I signal to determine the
duty cycle.
The two error signals, VEA.I and VEA.V, are compared with
an internal sawtooth waveform (VSAW) by PWM
comparators PWM.I and PWM.V to determine the duty
cycle. As shown in Figure 25, the outputs of two
comparators (PWM.I and PWM.V) are combined with an
OR gate and used as a reset signal of flip-flop to
determine the MOSFET turn-off instant. The lower
signal, VEA.V or VEA.I, determines the duty cycle, as
shown in Figure 25. During CV regulation, VEA.V
determines the duty cycle while VEA.I is saturated to
HIGH. During CC regulation, VEA.I determines the duty
cycle while VEA.V is saturated to HIGH.
Figure 24. Internal PWM Control Circuit
VEA.I
VEA.V
VEA.V
VEA.I
VSAW
Gate
PWM.V
PWM.I
OSC CLK
CV Regulation
CC Regulation
Figure 25. PWM Operation for CC and CV
Output Current Estimation
Figure 26 shows the key waveform of a flyback
converter operating in Discontinuous Conduction Mode
(DCM), where the secondary-side diode current reaches
zero before the next switching cycle begins. Since the
output current estimator is designed for DCM operation,
the power stage should be designed such that DCM is
guaranteed for the entire operating range. The output
current is obtained by averaging the triangular output
diode current area over a switching cycle:
IO
=< ID
>AVG = IPK
NP
NS
tDIS
2tS
(1)
where IPK is the peak value of the primary-side
current; NP and NS are the number of turns of
transformer primary-side and secondary-side,
respectively; tDIS is the diode current discharge time;
and tS is the switching period.
With a given current sensing resistor, the output current
can be programmed as:
IO
=
1 .25
K RSENSE
NP
NS
(2)
where K is the design parameter of IC, which is 10.5.
The peak value of primary-side current is obtained by an
internal peak detection circuit, while diode current
discharge time is obtained by detecting the diode
current zero-crossing instant. Since the diode current
cannot be sensed directly with primary-side control,
Zero Crossing Detection (ZCD) is accomplished
indirectly by monitoring the auxiliary winding voltage.
When the diode current reaches zero, the transformer
winding voltage begins to drop by the resonance
between the MOSFET output capacitance and the
transformer magnetizing inductance. To detect the
starting instant of the resonance, the VS is sampled at
85% of diode current discharge time of the previous
switching cycle, then compared with the instantaneous
VS voltage. When instantaneous VS drops below the
sampled voltage by more than 200mV, ZCD of diode
current is obtained, as shown in Figure 27.
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.1
10
www.fairchildsemi.com
 

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