Forcing the SDIO Line to the
Hi-Z State
There are times when the SDIO
line from the ADNS-2610 should
be in the Hi-Z state. For example,
if the microprocessor has com-
pleted a write to the ADNS-2610,
the SDIO line will go into a Hi-Z
state, because the SDIO pin was
configured as an input. However,
if the last operation from the
microprocessor was a read, the
ADNS-2610 will hold the D0 state
on SDIO until a falling edge of
SCK.
To place the SDIO pin into a Hi-Z
state, activate the power-down
mode by writing to the configura-
tion register. Then, the power-
down mode can stay activated,
with the ADNS-2610 in the
shutdown state, or the power-
down mode can be deactivated,
returning the ADNS-2610 to
normal operation. In both
conditions, the SDIO line will go
into the Hi-Z state.
PD
Timing
PD
Activated
32
clock
cycles
SDIO
10 ns, max
Hi-Z
Figure 24. SDIO Hi-z state and timing.
Another method to set the SDIO
line into the Hi-Z state, while
maintaining the ADNS-2610 at
normal mode, is to write any
data to an invalid address such
as 0x00 to address 0x77. The
SDIO line will go into the Hi-Z
state after the write operation.
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