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M38500E2 View Datasheet(PDF) - Renesas Electronics

Part Name
Description
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M38500E2
Renesas
Renesas Electronics Renesas
M38500E2 Datasheet PDF : 287 Pages
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HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0 Serial I/O1 status register
b7
(SIOSTS : address 001916)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns 1when read)
b7
b0 UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return 1when read)
Fig. 22 Structure of serial I/O1 control registers
sNotes on serial I/O
When setting the transmit enable bit of serial I/O1 to 1, the serial
I/O1 transmit interrupt request bit is automatically set to 1. When
not requiring the interrupt occurrence synchronized with the trans-
mission enalbed, take the following sequence.
Set the serial I/O1 transmit interrupt enable bit to 0(disabled).
Set the transmit enable bit to 1.
Set the serial I/O1 transmit interrupt request bit to 0after 1 or
more instructions have been executed.
Set the serial I/O1 transmit interrupt enable bit to 1(enabled).
b0
Serial I/O1 control register
(SIOCON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P24 to P27 operate as serial I/O1 pins)
1-26
3850 Group (Spec. H) Users Manual
 

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