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M38500E1-XXXFP View Datasheet(PDF) - Renesas Electronics

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Description
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M38500E1-XXXFP
Renesas
Renesas Electronics Renesas
M38500E1-XXXFP Datasheet PDF : 287 Pages
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HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H) uses the standard 740 Family instruc-
tion set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is 0, the high-order 8 bits becomes 0016. If
the stack page selection bit is 1, the high-order 8 bits becomes
0116.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b15
PCH
b7
b0
A
Accumulator
b7
b0
X
Index register X
b7
b0
Y
Index register Y
b7
b0
S
Stack pointer
b7
b0
PCL
Program counter
b7
b0
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
1-8
3850 Group (Spec. H) Users Manual
 

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