M38500E2 View Datasheet(PDF) - Renesas Electronics

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M38500E2

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

List of figures

Fig. 3.2.23 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-23

Fig. 3.2.24 CMOS output port P-channel side characteristics (Ta = 25 °C) ....................... 3-24

Fig. 3.2.25 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-24

Fig. 3.2.26 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .. 3-25

Fig. 3.2.27 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-25

Fig. 3.2.28 Definition of A-D conversion accuracy .................................................................. 3-26

Fig. 3.2.29 Flash memory version (M38507F8) A-D conversion standard characteristics .. 3-28

Fig. 3.2.30 Mask ROM version (M38503M2H, M38503M4H, M38504M6, M38507M8) A-D conversion

standard characteristics ............................................................................................. 3-29

Fig. 3.2.31 PROM version (M38504E6) A-D conversion standard characteristics ............. 3-30

Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-33

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-34

Fig. 3.3.3 Sequence of setting serial I/O1 control register again ......................................... 3-36

Fig. 3.3.4 Initialization of processor status register ................................................................ 3-40

Fig. 3.3.5 Sequence of PLP instruction execution .................................................................. 3-40

Fig. 3.3.6 Stack memory contents after PHP instruction execution ..................................... 3-40

Fig. 3.3.7 Status flag at decimal calculations .......................................................................... 3-41

Fig. 3.4.1 Selection of packages ............................................................................................... 3-43

Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-43

Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-44

Fig. 3.4.4 Wiring for CNVSS pin .................................................................................................. 3-44

Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version, the EPROM version, and the flash

memory version ................................................................................................................... 3-45

Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................ 3-45

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-46

Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-47

Fig. 3.4.9 Wiring of RESET pin ................................................................................................. 3-47

Fig. 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-48

Fig. 3.4.11 Setup for I/O ports ................................................................................................... 3-48

Fig. 3.4.12 Watchdog timer by software ................................................................................... 3-49

Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-50

Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50

Fig. 3.5.3 Structure of Serial I/O2 control register 1 .............................................................. 3-51

Fig. 3.5.4 Structure of Serial I/O2 control register 2 .............................................................. 3-51

Fig. 3.5.5 Structure of Serial I/O2 register ............................................................................... 3-52

Fig. 3.5.6 Structure of Transmit/Receive buffer register ........................................................ 3-52

Fig. 3.5.7 Structure of Seial I/O1 status register .................................................................... 3-53

Fig. 3.5.8 Structure of Seial I/O1 control register ................................................................... 3-54

Fig. 3.5.9 Structure of UART control register .......................................................................... 3-54

Fig. 3.5.10 Structure of Baud rate generator ........................................................................... 3-55

Fig. 3.5.11 Structure of PWM control register ......................................................................... 3-55

Fig. 3.5.12 Structure of PWM prescaler ................................................................................... 3-55

Fig. 3.5.13 Structure of PWM register ...................................................................................... 3-56

Fig. 3.5.14 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-56

Fig. 3.5.15 Structure of Timer 1 ................................................................................................ 3-57

Fig. 3.5.16 Structure of Timer 2 ................................................................................................ 3-57

Fig. 3.5.17 Structure of Timer XY mode register .................................................................... 3-58

Fig. 3.5.18 Structure of Timer X, Timer Y ............................................................................... 3-59

Fig. 3.5.19 Structure of Timer count source selection register ............................................. 3-59

Fig. 3.5.20 Structure of A-D control register ............................................................................ 3-60

Fig. 3.5.21 Structure of A-D conversion low-order register ................................................... 3-60

Fig. 3.5.22 Structure of A-D conversion high-order register .................................................. 3-61

3850 Group (Spec. H) User’s Manual

ix

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