ST90135M5Q6 View Datasheet(PDF) - STMicroelectronics

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ST90135M5Q6

8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM

STMicroelectronics 

ST90158 - INTERRUPTS

4.2.2 Segment Paging During Interrupt

Routines

The ENCSR bit in the EMR2 register can be used

to select between original ST9 backward compati-

bility mode and ST9+ interrupt management

mode.

ST9 backward compatibility mode (ENCSR = 0)

If ENCSR is reset, the CPU works in original ST9

compatibility mode. For the duration of the inter-

rupt service routine, ISR is used instead of CSR,

and the interrupt stack frame is identical to that of

the original ST9: only the PC and Flags are

pushed.

This avoids saving the CSR on the stack in the

event of an interrupt, thus ensuring a faster inter-

rupt response time.

It is not possible for an interrupt service routine to

perform inter-segment calls or jumps: these in-

structions would update the CSR, which, in this

case, is not used (ISR is used instead). The code

segment size for all interrupt service routines is

thus limited to 64K bytes.

ST9+ mode (ENCSR = 1)

If ENCSR is set, ISR is only used to point to the in-

terrupt vector table and to initialize the CSR at the

beginning of the interrupt service routine: the old

CSR is pushed onto the stack together with the PC

and flags, and CSR is then loaded with the con-

tents of ISR.

In this case, iret will also restore CSR from the

stack. This approach allows interrupt service rou-

tines to access the entire 4 Mbytes of address

space. The drawback is that the interrupt response

time is slightly increased, because of the need to

also save CSR on the stack.

Full compatibility with the original ST9 is lost in this

case, because the interrupt stack frame is differ-

ent.

ENCSR Bit

Mode

Pushed/Popp ed

Registers

Max. Code Size

for interrupt

service routine

0

ST9 Compatible

PC, FLAGR

64KB

Within 1 segment

1

ST9+

PC, FLAGR,

CSR

No limit

Across segments

4.3 INTERRUPT PRIORITY LEVELS

The ST9 supports a fully programmable interrupt

priority structure. Nine priority levels are available

to define the channel priority relationships:

– The on-chip peripheral channels and the eight

external interrupt sources can be programmed

within eight priority levels. Each channel has a 3-

bit field, PRL (Priority Level), that defines its pri-

ority level in the range from 0 (highest priority) to

7 (lowest priority).

– The 9th level (Top Level Priority) is reserved for

the Timer/Watchdog or the External Pseudo

Non-Maskable Interrupt. An Interrupt service

routine at this level cannot be interrupted in any

arbitration mode. Its mask can be both maskable

(TLI) or non-maskable (TLNM).

4.4 PRIORITY LEVEL ARBITRATION

The 3 bits of CPL (Current Priority Level) in the

Central Interrupt Control Register contain the pri-

ority of the currently running program (CPU priori-

ty). CPL is set to 7 (lowest priority) upon reset and

can be modified during program execution either

by software or automatically by hardware accord-

ing to the selected Arbitration Mode.

During every instruction, an arbitration phase

takes place, during which, for every channel capa-

ble of generating an Interrupt, each priority level is

compared to all the other requests (interrupts or

DMA).

If the highest priority request is an interrupt, its

PRL value must be strictly lower (that is, higher pri-

ority) than the CPL value stored in the CICR regis-

ter (R230) in order to be acknowledged. The Top

Level Interrupt overrides every other priority.

4.4.1 Priority level 7 (Lowest)

Interrupt requests at PRL level 7 cannot be ac-

knowledged, as this PRL value (the lowest possi-

ble priority) cannot be strictly lower than the CPL

value. This can be of use in a fully polled interrupt

environment.

4.4.2 Maximum depth of nesting

No more than 8 routines can be nested. If an inter-

rupt routine at level N is being serviced, no other

Interrupts located at level N can interrupt it. This

guarantees a maximum number of 8 nested levels

including the Top Level Interrupt request.

4.4.3 Simultaneous Interrupts

If two or more requests occur at the same time and

at the same priority level, an on-chip daisy chain,

specific to every ST9 version, selects the channel

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