ADCMP600BRJZ-R2 View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADCMP600BRJZ-R2

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators

Analog Devices 

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

Single-Supply TTL/CMOS Comparators

ADCMP600/ADCMP601/ADCMP602

FEATURES

Fully specified rail to rail at VCC = 2.5 V to 5.5 V

Input common-mode voltage from −0.2 V to VCC + 0.2 V

Low glitch CMOS-/TTL-compatible output stage

3.5 ns propagation delay

10 mW at 3.3 V

Shutdown pin

Single-pin control for programmable hysteresis and latch

Power supply rejection > 50 dB

Improved replacement for MAX999

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation

Clock and data signal restoration

Logic level shifting or translation

Pulse spectroscopy

High speed line receivers

Threshold detection

Peak and zero-crossing detectors

High speed trigger circuitry

Pulse-width modulators

Current/voltage-controlled oscillators

Automatic test equipment (ATE)

GENERAL DESCRIPTION

The ADCMP600, ADCMP601, and ADCMP602 are very fast

comparators fabricated on XFCB2, an Analog Devices, Inc.

proprietary process. These comparators are exceptionally

versatile and easy to use. Features include an input range from

GND − 0.5 V to VCC + 0.2 V, low noise, TTL-/CMOS-compatible

output drivers, and latch inputs with adjustable hysteresis

and/or shutdown inputs.

The device offers 5 ns propagation delay with 10 mV overdrive

on 3 mA typical supply current.

A flexible power supply scheme allows the devices to operate

with a single +2.5 V positive supply and a −0.5 V to +2.8 V

input signal range up to a +5.5 V positive supply with a −0.5 V

to +5.8 V input signal range. Split input/output supplies with no

sequencing restrictions on the ADCMP602 support a wide

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

INPUT

INVERTING

INPUT

ADCMP600/

ADCMP601/

ADCMP602

Q OUTPUT

LE/HYS SDN

(EXCEPT ADCMP600) (ADCMP602 ONLY)

Figure 1.

input signal range while still allowing independent output

swing control and power savings.

The TTL-/CMOS-compatible output stage is designed to drive

up to 5 pF with full timing specs and to degrade in a graceful

and linear fashion as additional capacitance is added. The

comparator input stage offers robust protection against large

input overdrive, and the outputs do not phase reverse when the

valid input signal range is exceeded. Latch and programmable

hysteresis features are also provided with a unique single-pin

control option.

The ADCMP600 is available in 5-lead SC70 and SOT-23

packages, the ADCMP601 is available in a 6-lead SC70 package,

and the ADCMP602 is available in an 8-lead MSOP package.

Rev. A

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.

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