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N25Q032A21ESF40F データシートの表示(PDF) - Micron Technology

N25Q032A21ESF40F Serial NOR Flash Memory 1.8V, Multiple I/O, 4KB Sector Erase Micron
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N25Q032A21ESF40F Datasheet PDF : 82 Pages
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32Mb, 1.8V, Multiple I/O Serial Flash Memory
Device Description
Device Description
The N25Q is the first high-performance multiple input/output serial Flash memory de-
vice manufactured on 65nm NOR technology. It features execute-in-place (XIP) func-
tionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus
interface. The innovative, high-performance, dual and quad input/output instructions
enable double or quadruple the transfer bandwidth for READ and PROGRAM opera-
The memory is organized as 64 (64KB) main sectors that are further divided into 16 sub-
sectors each (1024 subsectors in total). The memory can be erased one 4KB subsector at
a time, 64KB sectors at a time, or as a whole.
The memory can be write protected by software through volatile and nonvolatile pro-
tection features, depending on the application needs. The protection granularity is of
64KB (sector granularity) for volatile protections
The device has 64 one-time programmable (OTP) bytes that can be read and program-
med with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be
permanently locked with a PROGRAM OTP command.
The device also has the ability to pause and resume PROGRAM and ERASE cycles by us-
ing dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
Operating Protocols
The memory can be operated with three different protocols:
• Extended SPI (standard SPI protocol upgraded with dual and quad operations)
• Dual I/O SPI
• Quad I/O SPI
The standard SPI protocol is extended and enhanced by dual and quad operations. In
addition, the dual SPI and quad SPI protocols improve the data access time and
throughput of a single I/O device by transmitting commands, addresses, and data
across two or four data lines.
XIP Mode
XIP mode requires only an address (no instruction) to output data, improving random
access time and eliminating the need to shadow code onto RAM for fast execution.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods
are available. For applications that must enter XIP mode immediately after powering
up, XIP mode can be set as the default mode through the nonvolatile configuration reg-
ister bits.
PDF: 09005aef84566617
n25q_32mb_1_8v_65nm.pdf - Rev. E 6/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
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