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N25Q032A11EF840F View Datasheet(PDF) - Micron Technology

Part NameDescriptionManufacturer
N25Q032A11EF840F Serial NOR Flash Memory 1.8V, Multiple I/O, 4KB Sector Erase Micron
Micron Technology Micron
N25Q032A11EF840F Datasheet PDF : 82 Pages
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32Mb, 1.8V, Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 8
Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 8
Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9
Figure 5: Block Diagram ................................................................................................................................ 12
Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 17
Figure 7: SPI Modes ....................................................................................................................................... 17
Figure 8: Internal Configuration Register ........................................................................................................ 19
Figure 9: READ REGISTER Command ............................................................................................................ 29
Figure 10: WRITE REGISTER Command ......................................................................................................... 31
Figure 11: READ LOCK REGISTER Command ................................................................................................. 33
Figure 12: WRITE LOCK REGISTER Command ............................................................................................... 34
Figure 13: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 36
Figure 14: READ Command ........................................................................................................................... 40
Figure 15: FAST READ Command ................................................................................................................... 40
Figure 16: DUAL OUTPUT FAST READ ........................................................................................................... 41
Figure 17: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 41
Figure 18: QUAD OUTPUT FAST READ Command ......................................................................................... 42
Figure 19: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 42
Figure 20: PAGE PROGRAM Command .......................................................................................................... 44
Figure 21: DUAL INPUT FAST PROGRAM Command ...................................................................................... 45
Figure 22: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 45
Figure 23: QUAD INPUT FAST PROGRAM Command ..................................................................................... 46
Figure 24: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 47
Figure 25: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 49
Figure 26: SUBSECTOR and SECTOR ERASE Command .................................................................................. 51
Figure 27: BULK ERASE Command ................................................................................................................ 52
Figure 28: RESET ENABLE and RESET MEMORY Command ........................................................................... 55
Figure 29: READ OTP Command .................................................................................................................... 56
Figure 30: PROGRAM OTP Command ............................................................................................................ 58
Figure 31: XIP Mode Directly After Power-On .................................................................................................. 60
Figure 32: Power-Up Timing .......................................................................................................................... 62
Figure 33: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 65
Figure 34: Reset Enable ................................................................................................................................. 65
Figure 35: Serial Input Timing ........................................................................................................................ 65
Figure 36: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 66
Figure 37: Hold Timing .................................................................................................................................. 67
Figure 38: Output Timing .............................................................................................................................. 67
Figure 39: VPPH Timing .................................................................................................................................. 68
Figure 40: AC Timing Input/Output Reference Levels ...................................................................................... 70
Figure 41: UF-PDFN-8 4mm x 3mm (MLP8) – Package Code: F4 ...................................................................... 74
Figure 42: V-PDFN-8 6mm x 5mm (MLP8) – Package Code: F6 ........................................................................ 75
Figure 43: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 76
Figure 44: T-PBGA-240b05 6mm x 8mm – Package Code: 12 ............................................................................ 77
Figure 45: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 78
Figure 46: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 79
PDF: 09005aef84566617
n25q_32mb_1_8v_65nm.pdf - Rev. E 6/12 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
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