32Mb, 1.8V, Multiple I/O Serial Flash Memory
The signal description table below is a comprehensive list of signals for the N25 family
devices. All signals listed may not be supported on this device. See Signal Assignments
for information specific to this device.
Table 1: Signal Descriptions
Clock: Provides the timing of the serial interface. Commands, addresses, or data present at se-
rial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling
edge of the clock.
Chip select: When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in exten-
ded SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM,
ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode
(not deep power-down mode). Driving S# LOW enables the device, placing it in the active pow-
er mode. After power-up, a falling edge on S# is required prior to the start of any command.
Serial data: Transfers data serially into the device. It receives command codes, addresses, and
the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for
input/output during the following operations: DUAL OUTPUT FAST READ, QUAD OUTPUT FAST
READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for
output, data is shifted out on the falling edge of the clock.
In DIO-SPI, DQ0 always acts as an input/output.
In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE
cycle performed with VPP. The device temporarily enters the extended SPI protocol and then re-
turns to QIO-SPI as soon as VPP goes LOW.
Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of
the clock. DQ1 is used for input/output during the following operations: DUAL INPUT FAST
PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD
INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of
In DIO-SPI, DQ1 always acts as an input/output.
In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE
cycle performed with the enhanced program supply voltage (VPP). In this case the device tem-
porarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.
DQ2: When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the
signal functions as DQ2, providing input/output.
All data input drivers are always enabled except when used as an output. Micron recommends
customers drive the data signals normally (to avoid unnecessary switching current) and float
the signals before the memory device drives data on them.
DQ3: When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the
signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if
the device is selected.
RESET: This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the
normal operating mode. When RESET# is driven LOW, the memory enters reset mode and out-
put is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation
is in progress, data may be lost.
n25q_32mb_1_8v_65nm.pdf - Rev. E 6/12 EN
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