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AD15700BCA View Datasheet(PDF) - Analog Devices

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Description
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AD15700BCA
ADI
Analog Devices ADI
AD15700BCA Datasheet PDF : 44 Pages
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AD15700
16-BIT ADC TIMING CHARACTERISTICS (–40؇C to +85؇C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol Min
Typ
Max
Unit
Refer to Figures 14 and 15
Convert Pulsewidth
t1
Time between Conversions
t2
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
t3
BUSY HIGH All Modes Except in Master Serial Read after
t4
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t5
End of Conversion to BUSY LOW Delay
t6
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7
Acquisition Time
t8
RESET Pulsewidth
t9
5
1/1.25/1.5
2
10
1
10
ns
Note 1
ms
30
ns
0.75/1/1.25 ms
ns
ns
0.75/1/1.25 ms
ms
ns
Refer to Figures 16, 17, and 18 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t11
20
t12
t13
5
0.75/1/1.25 ms
ns
40
ns
15
ns
Refer to Figures 20 and 21 (Master Serial Interface Modes)2
CS_ADC LOW to SYNC Valid Delay
t14
CS_ADC LOW to Internal SCLK Valid Delay
t15
CS_ADC LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay (Read During Convert)
t17
(Warp Mode/Normal Mode/Impulse Mode)
10
ns
10
ns
10
ns
25/275/525
ns
SYNC Asserted to SCLK First Edge Delay 3
Internal SCLK Period3
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS_ADC HIGH to SYNC HI-Z
CS_ADC HIGH to Internal SCLK HI-Z
CS_ADC HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
CNVST LOW to SYNC Asserted Delay
Master Serial Read after Convert
t18
4
ns
t19
25
40
ns
t20
15
ns
t21
9
ns
t22
4.5
ns
t23
2
ns
t24
3
ns
t25
10
ns
t26
10
ns
t27
10
ns
t28
See Table II
ms
t29
0.75/1/1.25
ms
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figures 22 and 24 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5
External SCLK Active Edge to SDOUT Delay
t32
3
SDIN Setup Time
SDIN Hold Time
t33
5
t34
5
External SCLK Period
t35
25
External SCLK HIGH
External SCLK LOW
t36
10
t37
10
ns
16
ns
ns
ns
ns
ns
ns
NOTES
1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master Read during Convert Mode. See Table II.
Specifications subject to change without notice.
–4–
REV. A
 

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