ADDS-21160M-EZLITE View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADDS-21160M-EZLITE Datasheet PDF : 44 Pages
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AD15700
4R
IND
4R
INC
2R
INB
R
INA
REF
REFGND
INGND
32768C
MSB
16384C
4C
2C
LSB SWA
SWITCHES
CONTROL
C
C
65536C
COMP
SWB
CONTROL
LOGIC
CNVST
BUSY
OUTPUT
CODE
Figure 7. ADC Simplified Schematic
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4. . .VREF/65536). The control logic
toggles these switches, starting with the MSB first, in order to
bring the comparator back into a balanced condition. After the
completion of this process, the control logic generates the ADC
output code and brings BUSY output low.
Modes of Operation
The ADC features three modes of operation: warp, normal,
and impulse. Each of these modes is more suitable for specific
applications.
The warp mode allows the fastest conversion rate up to
1 MSPS. However, in this mode and this mode only, the full
specified accuracy is guaranteed only when the time between
conversion does not exceed 1 ms. If the time between two con-
secutive conversions is longer than 1 ms, for instance, after
power-up, the first conversion result should be ignored. This
mode makes the ADC ideal for applications where both high
accuracy and fast sample rate are required.
The normal mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. This mode makes
the ADC ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 666 kSPS. When operating at 100 SPS, for
example, it typically consumes only 15 mW. This feature makes
the ADC ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the ADC offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the ADC is shown in Figure 8 and Table III.
111...111
111...110
111...101
000...010
000...001
000...000
–FS
–FS + 1LSB
–FS + 0.5LSB
+FS – 1LSB
+FS – 1.5LSB
ANALOG INPUT
Figure 8. ADC Ideal Transfer Function
Table III. Output Codes and Ideal Input Voltages
Description
Analog Input
Digital Output Code
(Hexadecimal)
Straight Twos
Binary Complement
Full-Scale Range ± 10 V
Least Significant Bit 305.2 mV
FSR –1 LSB
9.999695 V
Midscale +1 LSB 305.2 mV
Midscale
0V
Midscale –1 LSB
–FSR +1 LSB
–305.2 mV
–9.999695 V
–FSR
–10 V
±5 V
± 2.5 V
0 V to 10 V
152.6 mV 76.3 mV
152.6 mV
4.999847 V 2.499924 V 9.999847 V
152.6 mV 76.3 mV
5.000153 V
0V
0V
5V
–152.6 mV –76.3 mV 4.999847 V
–4.999847 V –2.499924 V 152.6 mV
–5 V
–2.5 V
0V
0 V to 5 V
76.3 mV
4.999924 V
2.570076 V
2.5 V
2.499924 V
76.3 mV
0V
0 V to 2.5 V
38.15 mV
2.499962 V
1.257038 V
1.25 V
1.249962 V
38.15 mV
0V
FFFF1
8001
8000
7FFF
0001
00002
7FFF1
0001
0000
FFFF
8001
80002
NOTES
1This is also the code for an overrange analog input.
2This is also the code for an underrange analog input.
–28–
REV. A
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