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ADDS-2191-EZLITE View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADDS-2191-EZLITE
ADI
Analog Devices ADI
ADDS-2191-EZLITE Datasheet PDF : 44 Pages
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AD15700
ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42)
Pin No.
H9, J8,
J9, M12
M6
L7
Mnemonic
AGND_ADC
AVDD
BYTESWAP
L8
OB/2C
M7
WARP
L9
IMPULSE
M8
SER/PAR
M9, L10 D[0:1]
M10, L11 D[2:3] or
DIVSCLK[0:1]
M11
D[4] or EXT/INT
L12
D[5] or INVSYNC
K11
D[6] or INVSCLK
K12
D[7] or RDC/SDIN
J10
OGND
J11
OVDD
J12
DVDD
Type Description
P
Analog Power Ground Pin
P
DI
DI
DI
DI
DI
DO
DI/O
DI/O
DI/O
DI/O
DI/O
P
P
P
Input Analog Power Pin. Nominally 5 V.
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB
is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is
output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output
is straight binary; when LOW, the MSB is inverted, resulting in a twos complement
output from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH,
the Serial Interface Mode is selected and some bits of the DATA bus are used as a
serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these
outputs are in high impedance.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the
serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial
Port, are used to slow down, if desired, the internal serial clock that clocks the data output.
In the other serial modes, these inputs are not used.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital
select input for choosing the internal or an external data clock, called, respectively, Master
and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK
output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input and the external clock is gated by CS_ADC.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the
SCLK signal. It is active in both Master and Slave Mode.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an
external data input or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain
the conversion results from two or more ADCs onto a single SDOUT line. The digital
data level on SDIN is output on DATA with a delay of 16 SCLK periods after the
initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select
the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT
during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply as the supply of
the host interface (5 V or 3.3 V).
Digital Power. Nominally at 5 V.
REV. A
–11–
 

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