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MTV112MN32 View Datasheet(PDF) - Myson Century Inc

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MTV112MN32 Datasheet PDF : 20 Pages
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MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
= 0 Pin #37 is DA2.
P51E = 1 Pin #38 is P5.1.
= 0 Pin #38 is DA1.
P50E = 1 Pin #39 is P5.0.
= 0 Pin #39 is DA0.
MORE = 1 Bits P57E,P56E,P55E,P54E,P53E,P52E,P51E,P50E,DACK,EHALFV,
EHALFH,ENCLP,ADCMOD can be programmed,and master IIC speed is
controlled by (MCLK1,MCLK0) bits.
= 0 above bits internal keep “0” by MTV112M, and master IIC speed is controlled by
IICF bit.
* SINT0 should be 0 in this case.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
SFR is a group of registers that is the same as standard 8051.
2.2 Internal RAM
There is a 384 bytes RAM in MTV112M. The first portion of the RAM area contains 256 bytes, accessible by
setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.
2.3 External Special Function Registers (XFR)
XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for
monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access
these registers.
FFH Accessible by indirect
addressing only.
The value of PSW.1 =
both 0 and 1.
(Using MOV A, @Ri
80H
instruction)
7FH
Accessible by direct
and indirect
addressing.
PSW.1=0
00H
SFR
Accessible by direct
addressing.
Accessible by direct
and indirect
addressing.
PSW.1 =1
FFH
XFR
Accessible by indirect
external RAM
addressing.
(Using MOVX A, @Ri
00H
Instruction.)
3. PWM DAC
Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM clk
is X’tal or 2 * X’tal, selected by DACK. And the frequency of these DAC outputs is (PWM clk frequency)/253
or (PWM clk frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register
generates stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's
content is FFH. Writing 00H to the DAC register generates stable low output.
reg name addr
bit7
DA0 20h (r/w) DA0b7
DA1 21h (r/w) DA1b7
bit6
DA0b6
DA1b6
bit5
DA0b5
DA1b5
bit4
DA0b4
DA1b4
bit3
DA0b3
DA1b3
bit2
DA0b2
DA1b2
bit1
DA0b1
DA1b1
bit0
DA0b0
DA1b0
Revision 2.0
-5-
2001/05/18
 

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