ADRF6655
PLL CHARACTERISTIC
Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, loop filter = 1.5 kHz, unless
otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
1k
LO = 2275MHz
LO = 1100MHz
+25°C
–10°C
–40°C
+70°C
+85°C
10k
100k
1M
10M
100M
OFFSET FREQUENCY (kHz)
Figure 22. Typical Fractional-N Phase Noise Plot
0
1 × PFD OFFSET
–10 2 × PFD OFFSET
4 × PFD OFFSET
–20
+25°C
–40°C
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
–110
1050
1250
1450
1650
1850
2050
2250
LO FREQUENCY (MHz)
Figure 25. LO Reference/PFD Spurs vs. LO Frequency
1.0
+25°C
0.9
–10°C
–40°C
0.8
+70°C
+85°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
Figure 23.10 kHz to 40 MHz Integrated Phase Noise vs. LO Frequency
3.0
2.9
HIGH-SIDE LO
2.8
LOW-SIDE LO
2.7
+25°C
–40°C
+85°C
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
Figure 26. Tuning Voltage vs. LO Frequency
2500
2000
1500
1000
500
2.290G
–500
–1000
–1500
–2000
–2500
0
1: 10ms 2.289999883GHz
1
10
25
TIME (ms)
Figure 24. Lock Time for 10 MHz Step with 1.5 kHz Loop Filter
1.9
LO = 1100MHz, IP3SET = 3.2V
1.8
1.7
1.6
LO = 2300MHz, IP3SET = 3.2V
1.5
LO =2300MHz, IP3SET = OPEN
1.4
1.3
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 27. VPTAT MUXOUT Voltage vs. Temperature
Rev. 0 | Page 12 of 44