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LC72323 View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
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LC72323 Datasheet PDF : 13 Pages
First Prev 11 12 13
Continued from preceding page.
Operand
Mnemonic
1st 2nd
Function
AND
M I AND I with M
OR
M I OR I with M
EXL
LD
ST
MVRD
MVRS
MVSR
MVI
PLL
TMT
TMF
JMP
r M Exclusive OR M with r
r M Load M to r
M r Store r to M
Move M to destination
r M M referring to r in
the same row
Move source M
M r referring to r to M in
the same row
Move M to M in
M1 M2 the same row
M I Move I to M
Load M to PLL
M
r registers
Test M bits, then skip
M N if all bits specified
are true
Test M bits, then skip
M N if all bits specified
are false
ADDR Jump to the address
CAL
ADDR Call subroutine
RT
Return from subroutine
RTI
TTM
N
TUL
N
SS
N
Return from interrupt
Test timer F/F
then skip if it has
not been set
Test unlock F/F
then skip if it has
not been set
Set status register
RS
N
Reset status register
TST
N
Test status register true
TSF
N
Test status register false
LC72323
Operation
M (M) I
M (M) I
r (r) (M)
r (M)
M (r)
[DH, Rn] (M)
M [DH, Rn]
[DH, DL1] [DH, DL2]
MI
PLL r PLL DATA
if M (N) = all 1,
then skip
if M (N) = all 0,
then skip
PC ADDR
PC ADDR
Stack (PC) + 1
PC Stack
PC Stack
if timer F/F = 0,
then skip
if UL F/F = 0,
then skip
(Status register 1)
N1
(Status register 1)
N0
if (Status register 2) N =
all 1, then skip
if (Status register 2) N =
all 0, then skip
Machine code
D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0
0 0 1 1 0 0 DH
DL
I
0 0 1 1 1 0 DH
DL
I
0 0 1 0 0 0 DH
DL
Rn
1 0 0 0 0 0 DH
DL
Rn
1 0 0 0 0 1 DH
DL
Rn
1 0 0 0 1 0 DH
DL
Rn
1 0 0 0 1 1 DH
DL
Rn
1 0 0 1 0 0 DH
DL1
DL2
1 0 0 1 0 1 DH
DL
I
1 0 0 1 1 0 DH
DL
Rn
1 0 1 0 0 1 DH
DL
N
1 0 1 0 1 1 DH
DL
N
1011
ADDR (12 bits)
1100
ADDR (12 bits)
1 1 0 1 0 1 00 0000 000 0
1 1 0 1 0 1 01 0000 000 0
1 1 0 1 0 1 10 0000
N
1 1 0 1 0 1 11 0000
N
1 1 0 1 1 1 00 0000
N
1 1 0 1 1 1 01 0000
N
1 1 0 1 1 1 10 0000
N
1 1 0 1 1 1 11 0000
N
BANK
B
Select bank
BANK B
1 1 0 1 0 0 B 0000 000 0
Continued on next page.
No. 4950-12/13
 

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