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LC72323R View Datasheet(PDF) - SANYO -> Panasonic

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LC72323R Datasheet PDF : 13 Pages
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Pin Functions
Pin
Pin No.
LC72322R, 72323R
Functions
I/O
Low-threshold type dedicated input ports
PA0
30
These pins can be used, for example, for key data acquisition.
PA1
31
Built-in pull-down resistors can be specified as an option. This
Input
PA2
32
option is in 4-pin units, and cannot be specified for individual
PA3
33
pins.
Input through these pins is disabled in BACKUP mode.
PB0
35
PB1
36
Dedicated output ports
PB2
37
Since the output transistor impedances are unbalanced
PB3
38
CMOS, these pins can be effectively used for functions such
as key scan timing. These pins go to the output high-
PC0
39
impedance state in BACKUP mode.
PC1
40
These pins go to the low level during a reset, i.e., when the
PC2
41
RES pin is low.
PC3
42
Output
PD0
43
Dedicated output ports
PD1
44
These are normal CMOS outputs. These pins go to the output
high-impedance state in BACKUP mode.
PD2
45
These pins go to the low level during a reset, i.e., when the
PD3
46
RES pin is low.
PE0
PE1
PE2
PE3
PF0
PF1
PF2
PF3
PG0
PG1
PG2
PG3
I/O ports
These pins are switched between input and output as follows:
47
Once an input instruction (IN, TPT, or TPF) is executed, these
48
pins latch in the input mode. Once an output instruction (OUT,
SPB, or RPB) is executed, they latch in the output mode.
49
These pins go to the input mode during a reset, i.e., when the
50
RES pin is low.
In BACKUP mode these pins go to the input mode with input
disabled.
I/O
I/O ports
These pins are switched between input and output by the
51
FPC instruction.
52
The I/O states of this port can be specified for individual pins.
53
These pins go to the input mode during a reset, i.e., when the
54
RES pin is low.
In BACKUP mode these pins go to the input mode with input
disabled.
59
60
Dedicated input ports
61
Input through these pins is disabled in BACKUP mode.
62
Input
I/O circuit type
Continued on next page.
No. 5378-7/13
 

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