MC146818AP View Datasheet(PDF) - Motorola => Freescale
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MC146818AP Datasheet PDF : 20 Pages
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MC146818A
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Advance Information
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CMOS
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REAL-TIME CLOCK PLUS RAM (RTC)
The MC146818A Real-Time Clock plus RAM is a peripheral device
which includes the unique MOTEL concept for use with various
microprocessors, microcomputers, and larger computers. This part
combines three unique features: a complete time-of-day clock with
alarm and one hundred year calendar, a programmable periodic inter-
rupt and square-wave generator, and 50 bytes of low-power static
RAM. The MC146818A uses high-speed CMOS technology to interface
with 1 MHz processor buses, while consuming very little power.
The Real-Time Clock plus RAM has two distinct uses. First, it is
designed as a battery powered CMOS part (in an otherwise NMOS/TTL
system) including all the common battery backed-up functions such as
RAM, time, and calendar. Secondly, the MC146818A maybe used with
a CMOS microprocessor to relieve the software of the timekeeping ,~~
workload and to extend the available RAM of an MPU such as the ., “’~:$
MC146805E2.
q Low-Power, High-Speed CMOS
q Internal Time Base and Oscillator
O Counts Seconds, Minutes, and Hours of the Day
*$>+s)..q~>‘,,,&:$..~,.~;,.1,;.4~;,,$Q,,,\.:.>$*..,%~\*,$,{t~!i.!k!,s~F,p:..,.\~!..,\’.*\;.+.}.t
“’t:>?,.
q Counts Days of the Week, Date, Month, and Year
,$:
;<4 ,
q 3 V to 6 V Operation
~.t..!.k*,:$,:,.,
q Time
kHz
Base Input
Options:
4.194304
MHz,
1,.,0,:$,4,\,<8,.\,..t,.,.i,.%.Mi..,,;*)t.,$<~-f,.~*$~,z,
or 32.7W
q Time Base Oscillator for Parallel Resonan.~~$;\.$l..~{S]s
q 40 to 200 pW Typical Operating Power{,~L:~#~ ‘Frequency Time Base
q 4.0 to 20 mW Typical Operating Po,.~~$%.~j~,,*,$?gh Frequency Time Base
CASE 623
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q Binary or BCD Representation ~fTW~ Calendar, and Alarm
q 12- or 24-Hour Clock with ,A$~$:,$.>$,okQ.,.$?,P.{l+M<,
q Daylight Savings Time OplWn ‘$
*;* $*,,$$
q Automatic End of Mo~:~’’~$e6gnition
in 12-Hour Mode
q Automatic Leap Y~r ~&&~ensation
q Microprocessor#$@t~@‘.$$m*$patible
q Selectable B,a$-W~.&},y$n,~’W* otorola and Competitor Bus Timing
q Multiplex@:~@ fbr Pin Efficiency
~’.,-,,
q lnterfq&$&%@% Software as 64 RAM Locations
PIN ASSIGNMENT
‘oT ~vDD
Oscl [ 2
23 ] SQW
q 14 B~,e,*sJ:$’~CIOck and Control Registers
q ~’.~..~~.~~$i’of General Purpose RAM
@x;.$J&%wBsit indicates Data Integrity
?{&..us Compatible Interrupt Signals (~Q)
q Three Interrupts are Separately Software
Maskable and Testable
0SC2 [ 3
ADO [ 4
AD1 [ 5
AD2 [ 6
22 ] Ps
21 JCKOUT
20 ] CKFS
lg ] l~Q
Time-of-Day Alarm, Once-per-Second to Once-per-Day
Periodic Rates from 30.5 ps to 500 ms
End-of-Clock Update Cycle
q Programmable Square-Wave Output Signal
AD3 [ 7
AD4 [ 8
AD5 c g
18 ] RESET
17 ] DS
16 ] STBY
q Clock Output May Be Used as Microprocessor Clock Input
AD6 [ 10
15 ] Rl~
At Time Base Frequency -1
q 24-Pin Dual-In-Line Package
q Quad Pack Also Available
or +4
AD7 [ 11
Vss [ 12
14 ] AS
13 ]=
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hls document contains !ntormatlon on a new product. Specltlcatlons and tntormatlon here!n
are subject to change without notice
)MOTOROLAINC,, lW
ADI-1026
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