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T-ST508-DST-001 View Datasheet(PDF) - Unspecified

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T-ST508-DST-001 FM Tuner ETC
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T-ST508-DST-001 Datasheet PDF : 20 Pages
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T-ST508-DST-001
Data Sheet
RTC6218(RL508)
Mar. 2014
1.7. Control Interface
RL508 supports only I2C interface. Registers can be operated even RCLK is disappeared. VDD is required for register
operation.
1.7.1 2-wire Control Interface
For 2-wire I2C operation, SDIO and SCLK are operated in the open-drain, so external pull-up resistors are required on
PCB board. The transfer begins with START condition shown in Table 1. An 8-bits control word is defined in which is
A6, A5, A4, A3, A2, A1, A0 and R/W_ where A6:A0=1100100b and R/W_ = 1/0 means read/write operation. This
control word is internally latched on rising SCLK edge. To acknowledge control word, SDIO is driven low for one
cycle before the next falling SCLK edge.
For write operation (from HOST write to RL508), RL508 latches the incoming serial 8-bit data word on rising SCLK
edge. To acknowledge (ACK) each data word, SDIO is driven low for one cycle before the next falling SCLK edge.
Host can continue write the following data words with upper byte of register 02h first then lower byte of register 02h
until the last register is reached. Host can even further write the following data words because the internal address
counter automatically wraps around to the first register.
Data transfer completes when STOP condition happens to make internal address counter rest to 0. Refer to table 1 for
STOP condition.
For read operation (host read data from RL508), the serial 8-bit data word is shifted out at each falling SCLK edge and
following with acknowledge as Figure 4. Host can continuously read the following data words with upper byte of
register 0Ah first then lower byte of register 0Ah until the last register is reached. Host can even further read the
following data words because the internal address counter automatically wraps around to the first register. Host should
acknowledge each data word but send a non-acknowledge specifically after the data word that occurs before the STOP
condition. The internal address counter is reset to 0 when STOP condition happen.
Table 1. 2-Wire control interface characteristics
(VDD = 2 to 3.6 V TA = –20 to 85 °C)
PARAMETER
SYMBOL
SCLK Frequency
SCLK High Time
SCLK Low Time
Setup Time for START
Hold Time for START
SDIO Input to SCLK Setup
SDIO Input to SCLK Hold
Setup Time for STOP
STOP to START Time
SDIO Output to SCLK
SDIO, SCLK Rising Time
SDIO, SCLK Falling Time
SCLK, SDIO Capacitive
Loading
fSCL
tC1
tC2
tC3
tC4
tC5
tC6
tC7
tC8
tC9
tr
tf
Cb
TEST
CONDITION
MIN.
0
600
1300
600
600
100
100
600
1300
20 + 1*Cb
20 + 1*Cb
20 + 1*Cb
TYP. MAX.
400
900
250
300
300
50
UNIT
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Specifications subject to change without notice
8
Rev0.1
Confidential Proprietary
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