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AD9625BBPZ-2.0 View Datasheet(PDF) - Analog Devices

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AD9625BBPZ-2.0 Datasheet PDF : 56 Pages
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Data Sheet
Timing Diagrams
CLK–
CLK+
SYSREF–
SYSREF+
tSU_SR
CSB
tDS
tHIGH
tS
tDH
SCLK DON’T CARE
tH_SR
Figure 2. SYSREF± Setup and Hold Timing
tLOW
tCLK
AD9625
tH
DON’T CARE
SDIO DON’T CARE
R/W A14 A13 A12 A11 A10
A9
A8
A7
D5
D4
D3
D2
D1
D0 DON’T CARE
CLK+
(ENCODE CLOCK)
Figure 3. Serial Port Interface Timing Diagram (MSB First)
JESD204B INTERFACE
M = 1; L = 8; N = 12; N' = 16; CF = 0; CS = 0; CS = 0...4; K = 32; HD = 1; F = 1
500ps MIN (2.0GHz)
F = 1 OCTETS
SAMPLE N [11:4]
F = 1 OCTETS
SAMPLE N + 4 [11:4]
F = 1 OCTETS
SAMPLE N + 8 [11:4]
F = 1 OCTETS
SAMPLE N + 12 [11:4]
LANE A±
@ 5.0Gbps
fgh i jabcde fgh i jabcde fgh i jabcde fgh i jabcde fgh i j
SAMPLE N [3:0],
CCCC
SAMPLE N + 4 [3:0],
CCCC
SAMPLE N + 8 [3:0],
CCCC
SAMPLE N + 12 [3:0],
CCCC
LANE B±
@ 5.0Gbps
fgh i jabcde fgh i jabcde fgh i jabcde fgh i jabcde fgh i j
SAMPLE N + 1 [11:4]
SAMPLE N + 5 [11:4]
SAMPLE N + 9 [11:4]
SAMPLE N + 13 [11:4]
LANE C±
@ 5.0Gbps f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j
SAMPLE N + 1 [3:0],
CCCC
SAMPLE N + 5 [3:0],
CCCC
SAMPLE N + 9 [3:0],
CCCC
SAMPLE N + 13 [3:0],
CCCC
LANE D±
@ 5.0Gbps f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j
SAMPLE N + 2 [11:4]
SAMPLE N + 6 [11:4]
SAMPLE N + 10 [11:4]
SAMPLE N + 14 [11:4]
LANE E±
@ 5.0Gbps f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j
LANE F±
@ 5.0Gbps
SAMPLE N + 2 [3:0],
CCCC
SAMPLE N + 6 [3:0],
CCCC
SAMPLE N + 10 [3:0],
CCCC
SAMPLE N + 14 [3:0],
CCCC
fgh i jabcde fgh i jabcde fgh i jabcde fgh i jabcde fgh i j
SAMPLE N + 3 [11:4]
SAMPLE N + 7 [11:4]
SAMPLE N + 11 [11:4]
SAMPLE N + 15 [11:4]
LANE G± f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j
@ 5.0Gbps
SAMPLE N + 3 [3:0],
CCCC
SAMPLE N + 7 [3:0],
CCCC
SAMPLE N + 11 [3:0],
CCCC
SAMPLE N + 15 [3:0],
CCCC
LANE H± f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j
@ 5.0Gbps
Figure 4. CLK Input and DOUT Timing Relationship (Generic Eight-Lane Mode)
Rev. 0 | Page 7 of 56
 

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