ISL12024IRTCZ View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

ISL12024IRTCZ

Real-Time Clock/Calendar with Embedded Unique ID

Intersil 

ISL12024IRTCZ

sequential read mode. Since the clock runs continuously,

and a read takes a finite amount of time, there is the

possibility that the clock could change during the course of a

read operation. In this device, the time is latched by the read

command (falling edge of the clock on the ACK bit prior to

RTC data output) into a separate latch to avoid time changes

during the read operation. The clock continues to run.

Alarms occurring during a read are unaffected by the read

operation.

Writing to the Real-Time Clock

The time and date may be set by writing to the RTC

registers. RTC Register should be written ONLY with Page

Write. To avoid changing the current time by an incomplete

write operation, write to the all 8 bytes in one write operation.

When writing the RTC registers, the new time value is

loaded into a separate buffer at the falling edge of the clock

during the Acknowledge. This new RTC value is loaded into

the RTC Register by a stop bit at the end of a valid write

sequence. An invalid write operation aborts the time update

procedure and the contents of the buffer are discarded. After

a valid write operation, the RTC will reflect the newly loaded

data beginning with the next “one second” clock cycle after

the stop bit is written. The RTC continues to update the time

while an RTC register write is in progress and the RTC

continues to run during any non-volatile write sequences.

Accuracy of the Real-Time Clock

The accuracy of the real-time clock depends on the

accuracy of the quartz crystal that is used as the time base

for the RTC. Since the resonant frequency of a crystal is

temperature dependent, the RTC performance will also be

dependent upon temperature. The frequency deviation of

the crystal is a function of the turnover-temperature of the

crystal from the crystal’s nominal frequency. For example, a

>20ppm frequency deviation translates into an accuracy of

>1 minute per month. These parameters are available from

the crystal manufacturer. Intersil’s RTC family provides

on-chip crystal compensation networks to adjust

load-capacitance to tune oscillator frequency from -34ppm to

+80ppm when using a 12.5pF load crystal. For more detailed

information see the “Application Section” on page 20.

Clock/Control Registers (CCR)

The Control/Clock Registers are located in an area separate

from the EEPROM array, and are only accessible following a

slave byte of “1101111x”, and reads or writes to addresses

[0000h:003Fh]. The clock/control memory map has memory

addresses from 0000h to 003Fh. The defined addresses are

described in Table 1. Writing to and reading from the

undefined addresses are not recommended.

CCR Access

The contents of the CCR can be modified by performing a

byte or a page write operation directly to any address in the

CCR. Prior to writing to the CCR (except the status register),

however, the WEL and RWEL bits must be set using a three

step process (see section See “Writing to the Clock/Control

Registers” on page 12.)

The CCR is divided into 6 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (5 bytes; non-volatile)

4. Unique ID (8 bytes; non-volatile)

5. Real-Time clock (8 bytes; volatile)

6. Status (1 byte; volatile)

Each register is read and written through buffers. The

non-volatile portion (or the counter portion of the RTC) is

updated only if RWEL is set, and only after a valid write

operation and stop bit. A sequential read or page write

operation provides access to the contents of only one

section of the CCR per operation. Access to another section

requires a new operation. A read or write can begin at any

address in the CCR.

It is not necessary to set the RWEL bit prior to writing the

status register. Section 5 (status register) supports a single

byte read or write only. Continued reads or writes from this

section terminates the operation.

The state of the CCR can be read by performing a random

read at any address in the CCR at any time. This returns the

contents of that register location. Additional registers are

read by performing a sequential read. The read instruction

latches all Clock registers into a buffer, so an update of the

clock does not change the time being read. A sequential

read of the CCR will not result in the output of data from the

memory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus. After a

read of the CCR, the address remains at the previous

address +1 so the user can execute a current address read

of the CCR and continue reading the next Register.

Real-Time Clock Registers

SC, MN, HR, DT, MO, YR: Clock/Calendar Registers

These registers depict BCD representations of the time. As

such, SC (Seconds) and MN (Minutes) range from 00 to 59,

HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or

0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1

to 12, YR (Year) is 0 to 99.

DW: Day of the Week Register

This register provides a day of the week status, and uses

three bits DY2 to DY0 to represent the seven days of the

week. The counter advances in the cycle

0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value

to a specific day of the week is arbitrary, and may be decided

by the system software designer. The default value is

defined as ‘0’.

8

FN6749.0

August 8, 2008

Share Link: