AD9684-500EBZ View Datasheet(PDF) - Analog Devices
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AD9684-500EBZ Datasheet PDF : 64 Pages
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AD9684
VIN±x
SYNC+
SYNC–
CLK+
CLK–
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
N–1
APERTURE DELAY
N
N + 35
N + 36
N + 39
N + 40
N+x
N+y
N + 37
N + 38
N + 41
SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
tCLK
CONSTANT LATENCY = X CLK CYCLES
tDCO
tPD
FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE
DCO± (DATA CLOCK OUTPUT)
90° PHASE ADJUST1
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST2
STATUS+
(OVERRANGE/STATUS BIT)
STATUS–
D13±
STATUS STATUS
D13
D13
tSKEWR
tSKEWF
CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
[N]
[N + 1]
[N + 2]
[N + 3]
[N + 4]
STATUS STATUS STATUS STATUS STATUS
D13
D13
D13
D13
D13
D0±
D0
D0
D0
D0
D0
D0
D0
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data
Rev. 0 | Page 9 of 64
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